PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843001I-23 is a highly versatile, low
• One 3.3V LVPECL output pair and
ICS
HiPerClockS™
phase noise LVPECL/LVCMOS Synthesizer
which can generate low jitter reference clocks
for a variety of communication applications
and is a member of the HiPerClocksTM family
of high performance clock solutions from ICS.
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
The dual crystal interface allows the synthesizer to
support up to three communication standards in a given
application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb
Ethernet and Fibre Channel using a 25MHz crystal). The
rms phase jitter performance is typically less than 1ps, thus
making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
<1ps (typical) design target
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
3
N2:N0
Pulldown
SEL0
VCCO_LVCMOS
1
2
3
4
REF_OUT
VEE
OE_REF
M2
24
23
22
21
Pulldown
SEL1
N0
N1
N2
N
XTAL_IN0
000 ÷2
5
6
7
8
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
VCCO_LVPECL
20
19
18
17
16
15
14
13
001 ÷4
Q
nQ
VEE
OSC
00
01
11
010 ÷5
Q
011 ÷6
XTAL_OUT0
XTAL_IN1
VCCA
9
10
01
00
100 ÷8 (default)
101 ÷10
110 ÷12
111 ÷16
nQ
Phase
Detector
VCO
10
11
12
VCC
XTAL_OUT1
XTAL_IN1
OSC
XTAL_OUT1
CLK
M
ICS843001I-23
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
000 ÷44
Pulldown
10
11
001 ÷45
010 ÷48
011 ÷50
100 ÷51
G Package
TopView
111 ÷64 (default)
Pulldown
Pullup
MR
3
M2:M0
REF_OUT
Pulldown
OE_REF
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843001AGI-23
www.icst.com/products/hiperclocks.html
REV.B JANUARY 6, 2006
1