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ICS8430-111 PDF预览

ICS8430-111

更新时间: 2024-11-02 11:14:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
16页 181K
描述
700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8430-111 数据手册

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PRELIMINARY  
ICS8430-111  
Integrated  
Circuit  
Systems, Inc.  
700MHZ, LOW JITTER  
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8430-111 is a general purpose, dual out- Dual differential 3.3V LVPECL output  
ICS  
put high frequency synthesizer and a member of  
Selectable 14MHz to 27MHz differential CLK, nCLK  
orTEST_CLK input  
HiPerClockS™  
the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The CLK, nCLK pair  
can accept most standard differential input lev-  
CLK, nCLK accepts any differential input signal:  
LVPECL, LVHSTL, LVDS, SSTL, HCSL  
els. The single ended TEST_CLK input accepts LVCMOS or  
LVTTL input levels and translates them to 3.3V LVPECL levels.  
TheVCO operates at a frequency range of 200MHz to 700MHz.  
With the output configured to divide the VCO frequency by 2,  
output frequency steps as small as 2MHz can be achieved  
using a 16MHz differential or single ended reference clock. Out-  
put frequencies up to 700MHz can be programmed using the  
serial or parallel interfaces to the configuration logic. The low  
jitter and frequency range of the ICS8430-111 makes it an ideal  
clock generator for most clock tree applications.  
TEST_CLK accepts the following input types:  
LVCMOS, LVTTL  
Output frequency range up to 700MHz  
VCO range: 200MHz to 700MHz  
Parallel or serial interface for programming counter  
and output dividers  
Cycle-to-cycle jitter: 25ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Industrial termperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
CLK_SEL  
TEST_CLK  
0
32 31 30 29 28 27 26 25  
CLK  
1
M5  
M6  
M7  
M8  
N0  
N1  
N2  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CLK  
nCLK  
TEST_CLK  
CLK_SEL  
VCCA  
÷ 16  
ICS8430-111  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
MR  
VEE  
0
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
÷ N  
9
10 11 12 13 14 15 16  
÷ M  
1
÷ 2  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N2  
Y Package  
TopView  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8430DY-111  
www.icst.com/products/hiperclocks.html  
REV. F JUNE 1, 2005  
1

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