Datasheet > ICS842S104

ICS842S104

更新时间： 2024-11-02 05:39:03

品牌	Logo	应用领域
艾迪悌 - IDT		PC 时钟
页数	文件大小	规格书
21页	921K
描述
Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer

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ICS842S104 数据手册

Crystal-to-HSTL 100MHz / 200MHz

PCI Express™ Clock Synthesizer

ICS842S104

DATA SHEET

General Description

Features

The ICS842S104 is a PLL-based clock generator specifically

designed for PCI Express™ Clock Generation 2 applications. This

device generates either a 200MHz or 100MHz differential HSTL

clock from an input reference of 25MHz. The input reference may be

derived from an external source or by the addition of a 25MHz

crystal to the on-chip crystal oscillator. An external reference is

applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The

device offers spread spectrum clock output for reduced EMI

applications. An I²C bus interface is used to enable or disable spread

spectrum operation as well as select either a down spread value of

-0.35% or -0.5%.The ICS842S104 is available in a lead-free 24-Lead

package.

• Four differential HSTL output pairs

• Crystal oscillator interface: 25MHz

• Output frequency: 100MHz or 200MHz

• RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.27ps (typical)

• Cycle-to-cycle jitter: 25ps (maximum)

• I²C support with readback capabilities up to 400kHz

• Spread Spectrum for electromagnetic interference (EMI) reduction

• 3.3V core/1.5V to 2.0V output operating supply

• 0°C to 70°C ambient operating temperature

• Available lead-free (RoHS 6) package

• PCI Express Gen2 Jitter Compliant

HiPerClockS™

Block Diagram

Pin Assignment

SRCC4

SRCT4

SRCT3

SRCC3

V_SS

XTAL_IN ^25MHz

Divider

Network

SRCT[1:4]

SRCC[1:4]

OSC

PLL

VDDO

SDATA

XTAL_OUT

V_DDO

SRCT2

SRCC2

SRCT1

SCLK

XTAL_OUT

XTAL_IN

Pullup

SDATA

I²C

SCLK

Logic

SRCC1

V_SS

V_DD

V_SS

VDDA

VSS

ICS842S104

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

ICS842S104CG REVISION A MARCH 17, 2010

12 3 4 5 6 7...21

中文翻译

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