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ICS8427DY-02T PDF预览

ICS8427DY-02T

更新时间: 2024-11-02 11:14:35
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路时钟
页数 文件大小 规格书
21页 257K
描述
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER

ICS8427DY-02T 数据手册

 浏览型号ICS8427DY-02T的Datasheet PDF文件第2页浏览型号ICS8427DY-02T的Datasheet PDF文件第3页浏览型号ICS8427DY-02T的Datasheet PDF文件第4页浏览型号ICS8427DY-02T的Datasheet PDF文件第5页浏览型号ICS8427DY-02T的Datasheet PDF文件第6页浏览型号ICS8427DY-02T的Datasheet PDF文件第7页 
ICS8427-02  
500MHZ, LOW JITTER  
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8427-02 is a general purpose, six Six differential LVHSTL outputs  
ICS  
HiPerClockS™  
LVHSTL output high frequency synthesizer  
Selectable crystal input interface orTEST_CLK input  
and a member of the HiPerClockS™ family of  
High Performance Clock Solutions from ICS.  
The ICS8427-02 can support a very wide  
TEST_CLK accepts the following input types:  
LVCMOS, LVTTL  
output frequency range of 15.625MHz to 500MHz. The  
device powers up at a default output frequency of  
200MHz with a 16.6667MHz crystal interface, and the  
frequency can then be changed using the serial programm-  
ing interface to change the M feedback divider and N  
output divider. Frequency steps as small as 125kHz can  
be achieved using a 16.6667MHz crystal and the output  
divider set for ÷16.The low jitter and frequency range of the  
ICS8427-02 make it an ideal clock generator for most  
clock tree applications.  
Output frequency range: 15.625MHz to 500MHz  
VCO range: 250MHz to 500MHz  
Serial interface for programming feedback and output dividers  
Supports SSC, -0.5% downspread.Can be enabled through  
use of the serial programming interface.  
Output skew: 100ps (maximum)  
Cycle-to-cycle jitter: 50ps (maximum)  
2.5V core/1.8V output supply voltage  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
VCO_SEL  
XTAL_SEL  
PIN ASSIGNMENT  
TEST_CLK  
0
XTAL_IN  
1
OSC  
32 31 30 29 28 27 26 25  
XTAL_OUT  
÷ 16  
VDDO  
FOUT2  
nFOUT2  
VDDO  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL_OUT  
TEST_CLK  
XTAL_SEL  
VDDA  
PLL  
÷ 1,  
PHASE DETECTOR  
ICS8427-02  
FOUT3  
nFOUT3  
OE  
÷ 2,  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
÷ 4,  
0
÷ 8,  
VCO  
FOUT0  
nFOUT0  
MR  
÷ 16  
÷ M  
1
GND  
FOUT1  
÷ 2  
nFOUT1  
9
10 11 12 13 14 15 16  
FOUT2  
nFOUT2  
FOUT3  
nFOUT3  
FOUT4  
nFOUT4  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
FOUT5  
nFOUT5  
Y Package  
TopView  
OE  
S_LOAD  
S_DATA  
32-LeadVFQFN  
CONFIGURATION  
INTERFACE  
LOGIC  
5mm x 5mm x 0.75mm package body  
TEST  
S_CLOCK  
K Package  
TopView  
8427DY-02  
www.icst.com/products/hiperclocks.html  
REV.A FEBRUARY 17, 2006  
1

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