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ICS8422004AGIT PDF预览

ICS8422004AGIT

更新时间: 2024-11-02 11:14:35
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
13页 187K
描述
FEMTOCLOCKS? LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER

ICS8422004AGIT 数据手册

 浏览型号ICS8422004AGIT的Datasheet PDF文件第2页浏览型号ICS8422004AGIT的Datasheet PDF文件第3页浏览型号ICS8422004AGIT的Datasheet PDF文件第4页浏览型号ICS8422004AGIT的Datasheet PDF文件第5页浏览型号ICS8422004AGIT的Datasheet PDF文件第6页浏览型号ICS8422004AGIT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS8422004I  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKSLVCMOS/CRYSTAL-TO-  
LVHSTL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8422004I is a 4 output LVHSTL Synthesizer • Four LVHSTL outputs (VOHmax = 1.2V)  
ICS  
HiPerClockS™  
optimized to generate Fibre Channel reference  
clock frequencies and is a member of the  
HiPerClocksTM family of high performance clock  
solutions from ICS. Using a 26.5625MHz 18pF  
• Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
• Supports the following output frequencies: 212.5MHz,  
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz  
parallel resonant crystal, the following frequencies can be  
generated based on the 2 frequency select pins (F_SEL[1:0]):  
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz and  
53.125MHz. The ICS8422004I uses ICS’ 3rd generation low  
phase noise VCO technology and can achieve 1ps or lower  
typical rms phase jitter, easily meeting Fibre Channel jitter  
requirements. The ICS8422004I is packaged in a small  
24-pin TSSOP package.  
• VCO range: 560MHz - 680MHz  
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal  
(637kHz - 10MHz): 0.59ps (typical)  
• Power supply modes:  
Core/Output  
3.3V/1.8V  
2.5V/1.8V  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and lead-free RoHS-compliant  
packages  
FREQUENCY SELECT FUNCTION TABLE  
PIN ASSIGNMENT  
nQ1  
Q1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
nQ2  
Inputs  
Input  
Frequency  
(MHz)  
Output  
Frequency  
(MHz)  
2
3
4
Q2  
VDDO  
Q3  
M Divider N Divider  
M/N  
Divider Value  
VDDO  
Q0  
F_SEL1 F_SEL0  
Value  
24  
Value  
3
5
6
7
8
26.5625  
26.5625  
26.5625  
26.5625  
26.04166  
23.4375  
0
0
1
1
0
0
0
1
0
1
1
0
8
6
4
2
6
8
212.5  
159.375  
106.25  
53.125  
156.25  
187.5  
nQ3  
GND  
nc  
nQ0  
MR  
nPLL_SEL  
nc  
24  
24  
24  
24  
24  
4
6
nXTAL_SEL  
9
VDDA  
TEST_CLK  
GND  
XTAL_IN  
XTAL_OUT  
12  
4
10  
11  
12  
F_SEL0  
VDD  
F_SEL1  
3
ICS8422004I  
24-LeadTSSOP  
4.40mm x 7.8mm x 0.92mm  
BLOCK DIAGRAM  
F_SEL[1:0]  
Pulldown  
2
package body  
G Package  
TopView  
Pulldown  
nPLL_SEL  
Q0  
F_SEL[1:0]  
nQ0  
Pulldown  
TEST_CLK  
0 0 ÷3  
0 1 ÷4  
1 0 ÷6  
1 1 ÷12  
1
0
1
0
Q1  
26.5625MHz  
XTAL_IN  
nQ1  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
Q2  
Pulldown  
nXTAL_SEL  
nQ2  
M = 24 (fixed)  
Q3  
nQ3  
Pulldown  
MR  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8422004AGI  
www.icst.com/products/hiperclocks.html  
REV.B NOVEMBER 14, 2005  
1

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