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ICS8421004I-01 PDF预览

ICS8421004I-01

更新时间: 2024-11-18 11:14:35
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矽成 - ICSI /
页数 文件大小 规格书
13页 207K
描述
FEMTOCLOCKS? CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER

ICS8421004I-01 数据手册

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PRELIMINARY  
ICS8421004I-01  
FEMTOCLOCKS™ CRYSTAL-TO-  
HSTL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8421004I-01 is a 4 output HSTL • Four HSTL outputs (VOHmax = 1.4V)  
ICS  
Synthesizer optimized to generate Ethernet  
• Selectable crystal oscillator interface or  
reference clock frequencies and is a member of  
LVCMOS/LVTTL single-ended input  
HiPerClockS™  
the HiPerClocksTM family of high performance  
clock solutions from ICS. Using a 25MHz 18pF  
• Supports the following output frequencies: 156.25MHz,  
125MHz, 62.5MHz  
parallel resonant crystal, the following frequencies can be  
generated based on the 2 frequency select pins (F_SEL[1:0]):  
156.25MHz, 125MHz and 62.5MHz. The ICS8421004I-01  
uses ICS’ 3rd generation low phase noise VCO technology  
and can achieve 1ps or lower typical rms phase jitter, easily  
meeting Ethernet jitter requirements.The ICS8421004I-01 is  
packaged in a small 24-pin TSSOP package.  
• VCO range: 560MHz - 680MHz  
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal  
(1.875MHz - 20MHz): 0.44ps (typical)  
• Power supply modes:  
Core/Output  
3.3V/1.8V  
2.5V/1.8V  
• -40°C to 85°C ambient operating temperature  
FREQUENCY SELECT FUNCTION TABLE  
PIN ASSIGNMENT  
nQ1  
Q1  
1
24  
23  
22  
nQ2  
Q2  
Output  
Frequency  
(25MHz Ref.)  
2
M Divider N Divider  
M/N  
Divider Value  
3
4
5
6
7
8
9
10  
11  
12  
VDDO  
Q0  
VDDO  
Q3  
F_SEL1 F_SEL0  
Value  
Value  
21  
20  
19  
18  
17  
16  
15  
14  
13  
0
0
1
1
0
1
0
1
25  
4
6.25  
156.25  
125  
nQ0  
MR  
nPLL_SEL  
nc  
nQ3  
GND  
VDD  
nXTAL_SEL  
TEST_CLK  
GND  
25  
25  
25  
5
5
10  
2.5  
62.5  
VDDA  
not used  
not used  
F_SEL0  
VDD  
XTAL_IN  
F_SEL1  
XTAL_OUT  
ICS8421004I-01  
24-LeadTSSOP  
4.40mm x 7.8mm x 0.92mm  
BLOCK DIAGRAM  
F_SEL[1:0]  
Pulldown  
2
package body  
Pulldown  
nPLL_SEL  
G Package  
TopView  
Q0  
F_SEL[1:0]  
nQ0  
Pulldown  
TEST_CLK  
0 0 ÷4  
1
0
1
0
0 1 ÷5  
Q1  
25MHz  
XTAL_IN  
1 0 ÷10  
1 1 Not Used  
nQ1  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
Q2  
Pulldown  
nXTAL_SEL  
nQ2  
M = 25 (fixed)  
Q3  
nQ3  
Pulldown  
MR  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8421004AGI-01  
www.icst.com/products/hiperclocks.html  
REV. A MACH 29, 2005  
1

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