Datasheet > ICS650-21

ICS650-21

更新时间： 2022-12-01 12:20:15

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
4页	66K
描述
System Peripheral Clock Source

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ICS650-21 数据手册

PRELIMINARY INFORMATION

ICS650-21

System Peripheral Clock Source

Description

Features

The ICS650-21 is a low cost, low jitter, high

performance clock synthesizer for system

• Packaged in 20 pin tiny SSOP (QSOP)

• Lower jitter version of ICS650-01

• Operating VDD of 3.3V or 5V

• Zero ppm synthesis error in all clocks

• Inexpensive 25 MHz crystal or clock input

• Provides Ethernet and Fast Ethernet clocks

• Provides SCSI clocks

peripheral applications. Using analog/digital

Phase-Locked Loop (PLL) techniques, the device

accepts a parallel resonant 25 MHz crystal input to

produce up to eight output clocks. The device

provides clocks for PCI, SCSI, Fast Ethernet,

Ethernet, USB, and AC97. The user can select one

of three USB frequencies, and also one of two

AC97 audio frequencies. The OE pin puts all

outputs into a high impedance state for board level

testing. All frequencies are generated with less than

one ppm error, meeting the demands of SCSI and

Ethernet clocking.

• Provides PCI clocks

• Selectable AC97 audio clock

• Selectable USB clock

• OE pin tri-states the outputs for testing

• Selectable frequencies on three clocks

• Duty cycle of 45/55 for Processor clock and Audio

clock

The ICS650 can be mask customized to produce

any frequencies from 1 to 150 MHz.

Block Diagram

• Advanced, low power CMOS process

Processor Clocks

(Fast Ethernet,

SCSI, PCI )

Output

Buffer

PSEL1:0

Output

Buffer

ASEL

Audio Clock

Clock

Synthesis

Circuitry

Output

Buffers

USEL

USB Clock

25 MHz

crystal

or clock

X1/ICLK

Output

Buffers

20 MHz

25 MHz

Crystal

Oscillator

Output

Buffer

Output Enable (all outputs)

MDS 650-21 A

Revision 010301

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

12 3 4

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