Datasheet > ICS650-14B

ICS650-14B

更新时间： 2022-12-01 12:20:15

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
4页	49K
描述
Networking System Clock

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ICS650-14B 数据手册

PRELIMINARY INFORMATION

ICS650-14B

Networking System Clock

Description

Features

• Packaged in 20 pin (150 mil) SSOP (QSOP)

• 25.00 MHz fundamental crystal or clock input

• One fixed output clock of one 25.0 MHz

• One bank of four frequency selectable

output clocks

The ICS650-14B is a low cost, low jitter, high

performance clock synthesizer customized for

networking systems applications. Using analog

Phase-Locked Loop (PLL) techniques, the device

accepts a 25.0 MHz clock or fundamental mode

crystal input to produce multiple output clocks of

one fixed 25.0 MHz, a four (plus one) frequency

selectable bank, and two frequency selectable

clocks. All output clocks are frequency locked

together. The ICS650R-14B outputs

• Three frequency selectable clock outputs

• Zero ppm synthesis error in all clocks

• Ideal for networking systems

all have 0 ppm synthesis error.

• Full CMOS output swing

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

Block Diagram

• Industrial temperature range available

VDD GND

Output

Buffer

SELA 0:1

CLKA 1:4

SELB 0:1

SELC

Output

Buffer

Clock Synthesis

and Control

Circuitry

CLKA5

CLKB

CLKC

Output

Buffer

Output

Buffer

25.00 MHz

crystal or clock

X1/ICLK

Clock

Buffer/

Output

Buffer

25.00 MHz

Crystal

Oscillator

OE (All outputs)

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

MDS 650-14B A

Revision 082800

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com

12 3 4

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