Datasheet > ICS650-07C

ICS650-07C

更新时间： 2022-12-01 12:20:15

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
5页	77K
描述
Networking Clock Source

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ICS650-07C 数据手册

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

Description

Features

• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)

• 12.5 MHz or 25.00 MHz fundamental crystal or

clock input

The ICS650-07C is a low cost, low jitter, high

performance clock synthesizer for networking

applications. Using analog Phase-Locked Loop

(PLL) techniques, the device accepts a 12.5 MHz

or 25.00 MHz clock or fundamental mode crystal

input to produce multiple output clocks for

networking chips, PCI devices, SDRAM, and

ASICs. The ICS650-07C outputs all have 0 ppm

synthesis error.

• Six output clocks with selectable frequencies

• SDRAM frequencies of 67, 83, 100, and 133 MHz

• Buffered crystal reference output

• Zero ppm synthesis error in all clocks

• Ideal for PMC-Sierra’s ATM switch chips

• Full CMOS output swing with 25 mA output drive

capability at TTL levels

See the MK74CB214, ICS551, and ICS552-01 for

non-PLL buffer devices which produce multiple

low-skew copies of these output clocks.

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

See the ICS570, ICS9112-16/17/18 for zero delay

buffers that can synchronize outputs and other

needed clocks.

Block Diagram

VDD

GND

Output

CLKA1

Buffer

ACS1,0

BCS1,0

Output

÷ 2

CLKA2

CLKB1

CLKB2

CLKC1

CLKC2

REFOUT

Buffer

Clock Synthesis

and Control

Circuitry

Output

Buffer

Output

Buffer

CCS

Output

Buffer

12.5 MHz or

25.00 MHz

crystal or clock

Output

Buffer

Clock

Buffer/

Crystal

Output

Buffer

Oscillator

OE (all outputs)

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

12 3 4 5

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