Datasheet > ICS650-07B

ICS650-07B

更新时间： 2022-11-08 01:04:20

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
4页	41K
描述
Broadcom Clock Source

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ICS650-07B 数据手册

ICS650-07B

Broadcom Clock Source

Description

Features

The ICS650-07B is a low cost, low jitter, high

performance clock synthesizer customized for

Broadcom. Using analog Phase-Locked Loop

(PLL) techniques, the device accepts a 25.00 MHz

clock or fundamental mode crystal input to

produce multiple output clocks of 25.0 MHz, two

125.0 MHz, 133.33 MHz, and a selectable

33.3/66.6 MHz clock. All output clocks are

frequency locked together. The ICS650-07B

outputs all have 0 ppm synthesis error.

• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)

• 25.00 MHz fundamental crystal or clock input

• Four fixed output clocks of 25 MHz, 133.33 MHz,

and two copies of 125 MHz

• One selectable output clock of 33.3 or 66.6 MHz

• Zero ppm synthesis error in all clocks

• PCI clock switching occurs within 1 µs

• Ideal for Broadcom’s BCM5600 chipset

• Full CMOS output swing

Do not use the 125 MHz outputs to drive Gigabit

Ethernet SERDES. Instead, the 25 MHz clock

can be driven into our ICS601 in the X5 mode.

The ICS601 has low enough jitter and phase noise

for all popular SERDES.

• Advanced, low power, sub-micron CMOS process

• 3.0 V to 5.5 V operating voltage

Block Diagram

VDD GND

Output

PCI CLK

Buffer

Clock Synthesis

Output

Buffer

125.00 MHz

133.33 MHz

and Control

Circuitry

Output

Buffer

Output

Buffer

25.00 MHz

crystal or clock

Clock

Buffer/

Output

Buffer

25.00 MHz

Crystal

Oscillator

OE (all outputs)

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

MD S 650-07B A

Revision 042600

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

12 3 4

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