Datasheet > ICS571M

ICS571M

更新时间： 2024-09-16 22:51:31

品牌	Logo	应用领域
矽成 - ICSI		逻辑集成电路光电二极管驱动
页数	文件大小	规格书
4页	65K
描述
Low Phase Noise Zero Delay Buffer

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ICS571M 数据手册

PRELIMINARY INFORMATION

ICS571

Low Phase Noise Zero Delay Buffer

Description

Features

• Packaged in 8 pin SOIC.

The ICS571 is a high speed, high output drive, low

phase noise Zero Delay Buffer (ZDB) which

integrates ICS’ proprietary analog/digital Phase

Locked Loop (PLL) techniques. ICS introduced

the world standard for these devices in 1992 with

the debut of the AV9170, and updated that with

the ICS570. The ICS571, part of ICS’

ClockBlocks™ family, was designed to operate at

higher frequencies, with faster rise and fall times,

and with lower phase noise. The zero delay feature

means that the rising edge of the input clock aligns

with the rising edges of both outputs, giving the

appearance of no delay through the device. There

are two outputs on the chip, one being a low-skew

divide by two of the other.

• Can function as low phase noise x2 multiplier.

• Low skew outputs. One is ÷2 of other.

• Input clock frequency up to 160 MHz at 3.3V.

• Phase noise of better than -100 dBc/Hz from

1kHz to 1MHz offset from carrier

• Can recover poor input clock duty cycle.

• Output clock duty cycle of 45/55 at 3.3V.

• High drive strength for >100 MHz outputs.

• Full CMOS clock swings with 25mA drive

capability at TTL levels.

• Advanced, low power CMOS process.

• Operating voltages of 3.0 to 5.5 V.

The chip is ideal for synchronizing outputs in a

large variety of systems, from personal computers

to data communications to video. By allowing off-

chip feedback paths, the ICS571 can eliminate the

delay through other devices. The use of dividers in

the feedback path will enable the part to multiply

by more than two.

Block Diagram

Voltage

Output

Phase

Detector,

Charge

Pump, and

Loop Filter

ICLK

FBIN

CLK

Controlled

Oscillator

Buffer

÷2

Output

Buffer

CLK/2

External feedback can come from CLK or CLK/2 (see table on page 2).

MDS 571 B

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

12 3 4

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与ICS571M相关器件

型号	品牌	获取价格	描述	数据表
ICS571MLF	IDT	获取价格	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0
ICS571MLF	ICT	获取价格	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, L
ICS571MLFT	IDT	获取价格	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, L
ICS571MT	ICSI	获取价格	Low Phase Noise Zero Delay Buffer
ICS571MT	ICT	获取价格	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, S
ICS574	ICSI	获取价格	Zero Delay, Low Skew Buffer
ICS574M	ICSI	获取价格	Zero Delay, Low Skew Buffer
ICS574MI	IDT	获取价格	PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, S
ICS574MILF	IDT	获取价格	PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, L
ICS574MILFT	IDT	获取价格	PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, L