Datasheet > ICS558G-01

ICS558G-01

更新时间： 2024-11-07 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
5页	132K
描述
PECL/CMOS TO CMOS CLOCK DIVIDER

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ICS558G-01 数据手册

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

Description

Features

The ICS558-01 accepts a high speed input of either

• 16-pin TSSOP package

PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and

provides four CMOS low skew outputs. The chip also

has output enables so that one, three, or all four

outputs can be tri-stated.

• Available in Pb (lead) free package

• Selectable PECL or CMOS inputs

• Operates up to 250 MHz

• Works as a voltage translator

• Four low skew (<250 ps) outputs

The ICS558-01 is a member of the ICS Clock Blocks™

family of clock generation, synchronization, and

distribution devices.

• Selectable internal divider

• Operating input voltages of 3.3 V or 5.0 V

• Operating output voltages of 2.5 V, 3.3 V or 5.0 V

• Ideal for IA64 designs

Block Diagram

VDDP

VDDC

OE0

PECLIN

CLK1

CLK2

Output Divide

CMOSIN

SELPECL

S0, S1

CLK3

CLK4

OE1

GND

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5

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