Datasheet > ICS558-02

ICS558-02

更新时间： 2024-11-11 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
5页	120K
描述
LVHSTL TO CMOS CLOCK DIVIDER

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ICS558-02 数据手册

ICS558-02

LVHSTL TO CMOS CLOCK DIVIDER

Description

Features

The ICS558-02 accepts a high-speed LVHSTL input

and provides four CMOS low skew outputs from a

selectable internal divider (divide by 3, divide by 4). The

four outputs are split into two banks of two outputs.

Each bank has a separate output enable to tri-state the

output buffers.

• 16-pin TSSOP package

• LVHSTL inputs

• Accepts up to 250 MHz input frequency

• Four low skew (<250 ps) outputs

• Selectable internal divider of 3 or 4

• Operating voltage of 3.3 V

The ICS558-02 is a member of the ICS Clock Blocks

family of clock generation, synchronization, and

distribution devices.

Block Diagram

VDD

OE0

CLK1

CLK2

HCLK

Output Divide

/3 or /4

CLK3

CLK4

SEL

OE1

GND

MDS 558-02 D

Revision 020504

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5

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与ICS558-02相关器件

型号	品牌	获取价格	描述	数据表
ICS558-02T	IDT	获取价格	Prescaler/Multivibrator
ICS558AG-02	IDT	获取价格	Low Skew Clock Driver, 558 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4
ICS558AG-02LNT	IDT	获取价格	Low Skew Clock Driver, 558 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4
ICS558AG-02T	IDT	获取价格	Low Skew Clock Driver, 558 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4
ICS558G-01	ICSI	获取价格	PECL/CMOS TO CMOS CLOCK DIVIDER
ICS558G-01LF	ICSI	获取价格	PECL/CMOS TO CMOS CLOCK DIVIDER
ICS558G-01LFT	ICSI	获取价格	PECL/CMOS TO CMOS CLOCK DIVIDER
ICS558G-01T	ICSI	获取价格	PECL/CMOS TO CMOS CLOCK DIVIDER
ICS558G-02	ICSI	获取价格	LVHSTL TO CMOS CLOCK DIVIDER
ICS558G-02LFT	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, M