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ICS554GI-01AIT PDF预览

ICS554GI-01AIT

更新时间: 2024-11-11 20:11:15
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 175K
描述
Low Skew Clock Driver, 554 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, TSSOP-16

ICS554GI-01AIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, 0.65 MM PITCH, TSSOP-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.14系列:554
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
最小 fmax:200 MHzBase Number Matches:1

ICS554GI-01AIT 数据手册

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DATASHEET  
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT  
ICS554-01A  
Description  
Features  
The ICS554-01A is a low skew clock buffer with a single  
complimentary PECL input to four PECL outputs. Part of  
ICS’ Clock Blocks family, this is our lowest skew PECL  
Input frequency up to 200 MHz  
Advanced CMOS process  
TM  
Outputs are skew matched to within 50 ps  
Packaged in 16-pin TSSOP  
clock buffer. The ICS554-01A is footprint compatible with  
the ICS554-01, but requires fewer passive components for  
termination thus providing a cost-saving alternative. For  
parts which do not require PECL inputs or outputs, see the  
ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a  
1 to 8 low skew buffer. For more than 8 outputs see the  
One PECL input to 4 PECL output clock drivers  
Operating Voltages of 3.3 V or 5 V  
Industrial temperature range  
TM  
MK74CBxxx Buffalo series of clock drivers.  
Functional equivalent to ICS554-01  
Simplified passive termination network compared to  
ICS554-01  
ICS makes many non-PLL and PLL based low skew output  
devices as well as Zero Delay Buffers to synchronize  
clocks. Contact us for all of your clocking needs.  
Block Diagram  
VDD  
IN  
IN  
Q0  
Q0  
Q1  
Q1  
Q2  
Q2  
Q3  
Q3  
VSS  
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT  
1
ICS554-01A  
REV B 070606  

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