Datasheet > ICS527-02

ICS527-02

更新时间： 2024-11-06 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
8页	159K
描述
Clock Slicer User Configurable PECL Input Zero Delay Buffer

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ICS527-02 数据手册

ICS527-02

Clock Slicer User Configurable PECL Input Zero Delay Buffer

Description

Features

The ICS527-02 Clock Slicer is the most flexible way to

generate a CMOS output clock from a PECL input

clock with zero skew. The user can easily configure the

device to produce nearly any output clock that is

multiplied or divided from the input clock. The part

supports non-integer multiplications and divisions. A

SYNC pulse indicates when the rising clock edges are

aligned with zero skew. Using Phase-Locked Loop

(PLL) techniques, the device accepts an input clock up

to 200 MHz and produces an output clock up to 160

MHz.

• Packaged as 28-pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• PECL IN to CMOS OUT

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency—no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz to 200 MHz

• Output clock frequencies from 2.5 MHz to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

The ICS527-02 aligns rising edges on PECLIN with

FBIN at a ratio determined by the reference and

feedback dividers.

For a PECL input and output clock with zero delay, use

the ICS527-04.

• Advanced, low-power CMOS process

• Industrial temperature version available

For a CMOS input and PECL output with zero delay,

use the ICS527-03.

Block Diagram

R6:R0

VDD

PECLIN

Reference

Divider

33 ohm

CLK1

Phase Comparator,

Charge Pump, and

Loop Filter

Output

Divider

VCO

Divide

by 2

33 ohm

FBIN

Feedback

Divider

CLK2

SYNC

Feedback can

come from

CLK1 or CLK2

(not both)

GND

DIV2

PDTS

F6:F0

S1:S0

MDS 527-02 F

Revision 022806

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7 8

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与ICS527-02相关器件

型号	品牌	获取价格	描述	数据表
ICS527-03	ICSI	获取价格	Clock Slicer User Configurable PECL Output Zero Delay Buffer
ICS527-04	ICSI	获取价格	Clock Slicer User Configurable PECL input Zero Delay Buffer
ICS527R-01	ICSI	获取价格	Clock Slicer⑩ User Configurable Zero Delay Bu
ICS527R-01I	ICSI	获取价格	Clock Slicer⑩ User Configurable Zero Delay Bu
ICS527R-01IT	ICSI	获取价格	Clock Slicer⑩ User Configurable Zero Delay Bu
ICS527R-01T	ICSI	获取价格	Clock Slicer⑩ User Configurable Zero Delay Bu
ICS527R-02	ICSI	获取价格	Clock Slicer User Configurable PECL Input Zero Delay Buffer
ICS527R-02I	ICSI	获取价格	Clock Slicer User Configurable PECL Input Zero Delay Buffer
ICS527R-02ILFT	IDT	获取价格	PLL Based Clock Driver, 527 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO28,
ICS527R-02IT	ICSI	获取价格	Clock Slicer User Configurable PECL Input Zero Delay Buffer