Datasheet > ICS503MT

ICS503MT

更新时间： 2024-09-12 22:48:19

品牌	Logo	应用领域
矽成 - ICSI		晶体外围集成电路光电二极管时钟
页数	文件大小	规格书
4页	64K
描述
LOCO⑩ PLL Clock Multiplier

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ICS503MT 数据手册

PRELIMINARY INFORMATION

ICS503

LOCO™ PLL Clock Multiplier

Description

Features

• Packaged as 8 pin SOIC or die

The ICS503 is a member of the LOCO™ family,

the most cost effective way to generate a high

quality, high frequency clock output from a low

frequency crystal or clock input. The name LOCO

stands for LOw Cost Oscillator, as it is designed

to replace crystals and crystal oscillators in most

electronic systems. Using Phase-Locked-Loop

(PLL) techniques, the device uses a standard

fundamental mode, inexpensive crystal to produce

output clocks up to 160 MHz.

• ICS’ lowest cost PLL clock family

• Generates 16.9344 MHz for stereo codecs from

the 14.31818 MHz motherboard clock

• Can be cost effective in replacing a single

surface-mount crystal

• Can be driven by other 5xx series

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 2 - 50 MHz

• Output clock frequencies up to 160 MHz

• Low jitter - 50 ps one sigma

Stored in the chip’s ROM is the ability to generate

9 different multiplication factors, allowing one

chip to be used in two or three different

applications (see page 2).

• Duty cycle of 45/55 up to 160 MHz

• Operating voltages of 3.0 to 5.5V

• Full CMOS level outputs with 25mA drive

capability at TTL levels

• Advanced, low power CMOS process

Block Diagram

VDD GND

PLL

Clock Multiplier

Circuitry

and

Output

Buffer

Crystal or

clock input

CLK

X1/ICLK

Crystal

Oscillator

ROM

Optional crystal capacitors

MDS 503 A

Revision 111000

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com

12 3 4

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