Datasheet > ICS487G-25LFT

ICS487G-25LFT

更新时间： 2024-11-14 11:14:27

品牌	Logo	应用领域
矽成 - ICSI		晶体外围集成电路电视光电二极管时钟
页数	文件大小	规格书
6页	147K
描述
Quad PLL for DTV

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ICS487G-25LFT 数据手册

ICS487-25

Quad PLL for DTV

Description

Features

The ICS487-25 generates five high-quality,

high-frequency clock outputs. It is designed to replace

crystals and crystal oscillators in DTV applications.

Using ICS’ patented Phase Locked Loop (PLL)

techniques, the device runs from a lower frequency

crystal or clock input.

• Packaged in 16-pin TSSOP

• Available in Pb-free packaging

• Replaces multiple crystals and oscillators

• Input crystal or clock frequency of 27 MHz

• Zero ppm frequency synthesis error

• Duty cycle of 45/55

Because there is zero ppm frequency synthesis error

on the audio clocks, the audio will remain locked to the

video.

• Operating voltage of 3.3 V

• Advanced, low power CMOS process

Block Diagram

VDD

S1:0

PLL1

PLL2

PLL3

ACLK

20M

48M

33.0M

X1/ICLK

27 MHz

clock or

crystal

input

Crystal

Oscillator/

Clock

PLL4

24.576M

Buffer

External capacitors

may be required.

PDTS (all outputs and PLLs)

GND

MDS 487-25 A

Revision 050604

Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com

12 3 4 5 6

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