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ICS43002A41 PDF预览

ICS43002A41

更新时间: 2024-11-14 11:14:27
品牌 Logo 应用领域
矽成 - ICSI 石英晶振压控振荡器衰减器
页数 文件大小 规格书
21页 277K
描述
700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

ICS43002A41 数据手册

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PRELIMINARY  
ICS843002I-41  
Integrated  
Circuit  
Systems, Inc.  
700MHZ, FEMTOCLOCKS™ VCXO BASED  
SONET/SDH JITTER ATTENUATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS843002I-41 is a member of the (2) Differential LVPECL outputs  
ICS  
HiperClockS™ family of high performance clock  
solutions from ICS.The ICS843002I-41 is a PLL  
based synchronous clock generator that is  
optimized for SONET/SDH line card applications  
Selectable CLKx, nCLKx differential input pairs  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or  
single-ended LVCMOS or LVTTL levels  
where jitter attenuation and frequency translation is needed.  
The device contains two internal PLL stages that are cascaded  
in series.The first PLL stage uses a VCXO which is optimized  
to provide reference clock jitter attenuation and to be jitter  
tolerant, and to provide a stable reference clock for the 2nd  
PLL stage (typically 19.44MHz). The second PLL stage  
provides additional frequency multiplication (x32), and it  
maintains low output jitter by using a low phase noise  
FemtoClock™ VCO. PLL multiplication ratios are selected  
from internal lookup tables using device input selection pins.  
The device performance and the PLL multiplication ratios are  
optimized to support non-FEC (non-Forward Error Correction)  
SONET/SDH applications with rates up to OC-48 (SONET)  
Maximum output frequency: 700MHz  
FemtoClock VCO frequency range: 560MHz - 700MHz  
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal  
(12kHz to 20MHz): 0.81ps (typical)  
Full 3.3V or mixed 3.3V core/2.5V output supply voltage  
-40°C to 85°C ambient operating temperature  
or STM-16 (SDH).The VCXO requires the use of an external, PIN ASSIGNMENT  
inexpensive pullable crystal.VCXO PLL uses external passive  
loop filter components which are used to optimize the PLL  
loop bandwidth and damping characteristics for the given  
line card application.  
The ICS843002I-41 includes two clock input ports. Each one  
can accept either a single-ended or differential input. Each  
input port also includes an activity detector circuit, which  
reports input clock activity through the LOR0 and LOR1 logic  
output pins.The two input ports feed an input selection mux.  
“Hitless switching” is accomplished through proper filter  
tuning. Jitter transfer and wander characteristics are  
influenced by loop filter tuning, and phase transient  
performance is influenced by both loop filter tuning and  
alignment error between the two reference clocks.  
32 31 30 29 28 27 26 25  
LF1  
LF0  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
LOR0  
LOR1  
nc  
ISET  
VCC  
VCCO_LVCMOS  
VCCO_LVPECL  
nQB  
CLK0  
nCLK0  
CLK_SEL  
QB  
QA_SEL2  
VEE  
9
10 11 12 13 14 15 16  
Typical ICS843002I-41 configuration in SONET/SDH Systems:  
VCXO 19.44MHz crystal  
Loop bandwidth: 50Hz - 250Hz  
Input Reference clock frequency selections:  
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,  
311.04MHz, 622.08MHz  
ICS843002I-41  
32-LeadVFQFN  
Output clock frequency selections:  
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz,  
622.08MHz, Hi-Z  
5mm x 5mm x 0.75mm package body  
K Package  
TopView  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
843002AKI-41  
www.icst.com/products/hiperclocks.html  
REV. A JUNE 1, 2005  
1

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