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ICS309RI

更新时间: 2024-11-10 22:48:15
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
8页 133K
描述
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTHESIZER

ICS309RI 数据手册

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ICS309  
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTHESIZER  
Description  
Features  
The ICS309 is a versatile serially-programmable, triple  
PLL with spread spectrum clock source. The ICS309  
can generate any frequency from 250kHz to 200 MHz,  
and up to 6 different output frequencies simultaneously.  
The outputs can be reprogrammed on-the-fly, and will  
lock to a new frequency in 10 ms or less.  
Packaged in 20-pin SSOP (QSOP)  
Highly accurate frequency generation  
M/N Multiplier PLL: M = 1..2048, N = 1..1024  
Serially programmable: user determines the output  
frequency via a 3-wire interface  
Spread Spectrum frequency modulation for reduced  
To reduce system EMI emissions, spread spectrum is  
available that supports modulation frequencies of  
31 kHz and 120 kHz, as well as modulation amplitudes  
of +/-0.25% to +/-2.0%. Both center and down-spread  
options are available.  
system EMI  
Center or Down Spread up to 4% total  
Selectable 32 kHz and 120 kHz modulation  
Eliminates need for custom quartz oscillators  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 3 - 50 MHz  
Output clock frequencies up to 200 MHz  
Operating voltage of 3.3 V  
The device includes a PDTS pin which tri-states the  
output clocks and powers down the entire chip.  
The ICS309 default for non-programmed start-up are  
buffered reference clock outputs on all clock output  
pins.  
TM  
ICS’ VersaClock programming software allows the  
Up to 9 reference clock outputs  
Power down tri-state mode  
user to configure up to 9 outputs with target  
frequencies, spread spectrum capabilities or buffered  
TM  
reference clock outputs. The VersaClock software  
Very low jitter  
automatically configures the PLLs for optimal overall  
performance.  
Block Diagram  
3
VDD  
PLL1 with  
Spread  
Spectrum  
CLK1  
CLK2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
STROBE  
SCLK  
DATA  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
2
External capacitors are  
required with a crystal input.  
PDTS  
MDS 309 G  
1
Revision 122704  
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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