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ICS291PGI

更新时间: 2024-09-15 11:14:23
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
8页 170K
描述
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer

ICS291PGI 数据手册

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PRELIMINARY INFORMATION  
ICS291  
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer  
Description  
Features  
The ICS291 field programmable spread spectrum clock  
synthesizer generates up to six high-quality,  
high-frequency clock outputs including multiple  
reference clocks from a low-frequency crystal input. It  
is designed to replace crystals, crystal oscillators and  
stand alone spread spectrum devices in most  
electronic systems.  
Packaged as 20-pin TSSOP  
Eight addressable registers  
Replaces multiple crystals and oscillators  
Output frequencies up to 200 MHz at 3.3 V  
Configurable Spread Spectrum Modulation  
Input crystal frequency of 5 to 27 MHz  
Clock input frequency of 3 to 166 MHz  
Up to six reference outputs  
TM  
Using ICS’ VersaClock software to configure PLLs  
and outputs, the ICS291 contains a One-Time  
Programmable (OTP) ROM for field programmability.  
Programming features include input/output  
frequencies, spread spectrum amount, eight selectable  
configuration registers and up to two sets of three  
low-skew outputs.  
Separate 1.8 to 3.3 V VDDO output level controls for  
each bank of 3 outputs  
Up to two sets of three low-skew outputs  
Operating voltages of 3.3 V  
Each of the two output groups are powered by a  
separate VDDO voltage. VDDO may vary from 1.8 V to  
VDD.  
Controllable output drive levels  
Advanced, low-power CMOS process  
Available in Pb (lead) free packaging  
Using Phase-Locked Loop (PLL) techniques, the  
device runs from a standard fundamental mode,  
inexpensive crystal, or clock. It can replace multiple  
crystals and oscillators, saving board space and cost.  
The ICS291 is also available in factory programmed  
custom versions for high-volume applications.  
Block Diagram  
VDDO1  
3
VDD  
PLL1 with  
Spread  
Spectrum  
3
S2:S0  
OTP  
CLK1  
CLK2  
CLK3  
ROM  
with PLL  
Values  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
CLK4  
CLK5  
CLK6  
X1/ICLK  
Crystal  
Oscillator  
Crystal or  
Clock Input  
X2  
3
External capacitors  
are required with a crystal input.  
GND  
VDDO2  
PDTS  
MDS 291 C  
1
Revision 062205  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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