Datasheet > ICS2402MT

ICS2402MT

更新时间： 2024-09-15 04:22:51

品牌	Logo	应用领域
矽成 - ICSI		逻辑集成电路光电二极管驱动
页数	文件大小	规格书
7页	134K
描述
Multiplier and Zero Delay Buffer

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ICS2402MT 数据手册

ICS2402

Multiplier and Zero Delay Buffer

Description

Features

The ICS2402 is a high-performance Zero Delay Buffer

(ZDB) which integrates ICS’ proprietary analog/digital

Phase-Locked Loop (PLL) techniques. The chip is part

• 8-pin SOIC package

• Available in Pb (lead) free package

• Absolute jitter 100 ps

• Propagation Delay of 600 ps

• Output multiplier of 2X

• Output clock frequency up to 80 MHz

• Can recover degraded input clock duty cycle

• Output clock duty cycle of 45/55

of ICS’ ClockBlocks family and was designed as a

performance upgrade to meet today’s higher speed and

lower voltage requirements. The zero delay feature

means that the rising edge of the input clock aligns with

the rising edges of both output clocks, giving the

appearance of no delay through the device.

• Full CMOS clock swings with 25 mA drive capability

The ICS2402 is ideal for synchronizing outputs in a

large variety of systems, from personal computers to

data communications to graphics/video. By allowing

off-chip feedback paths, the device can eliminate the

delay through other devices.

at TTL levels

• Advanced, low power CMOS process

• Operating voltage of 3.3 V or 5 V

Block Diagram

Phase

ICLK

Detector,

Charge

Pump,

and

Loop

VCO

CLK1

Filter

divide

FBIN

by N

MDS 2402 D

Revision 122104

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7

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