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ICS1893AGI PDF预览

ICS1893AGI

更新时间: 2024-01-25 05:44:38
品牌 Logo 应用领域
矽成 - ICSI 电信集成电路光电二极管
页数 文件大小 规格书
135页 1373K
描述
3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM

ICS1893AGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DFN
包装说明:HVQCCN, LCC56,.31SQ,20针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.31
Is Samacsys:N数据速率:100000 Mbps
JESD-30 代码:S-PQCC-N56JESD-609代码:e3
长度:8 mm湿度敏感等级:3
功能数量:1端子数量:56
收发器数量:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC56,.31SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Network Interfaces最大压摆率:0.16 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:INTERFACE CIRCUIT
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:8 mmBase Number Matches:1

ICS1893AGI 数据手册

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Integrated Circuit Systems, Inc.  
Document Type: Data Sheet  
Document Stage: Preliminary  
ICS1893AG  
3.3 V 10Base-T/100Base-TX Integrated PHYceiver™  
General  
Features  
The ICS1893AG is a re-packaged version of the ICS1893AF  
in a 56-lead TSSOP 240 mil package. The ICS1893AG is a  
fully integrated, Physical Layer device (PHY) that is  
compliant with both the 10Base-T and 100Base-TX  
CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The  
ICS1893AG uses the same proven silicon as the  
ICS1893AF but offers a smaller form factor solution to users  
where physical package size is important.  
Single 3.3 V ±10% power supply  
Supports category 5 cables with attenuation in excess of  
24dB at 100 MHz across a temperature range from 0°C to  
+70°C. Industrial temperature version is also available.  
DSP-based baseline wander correction to virtually  
eliminate killer packets  
Low-power, 0.35-micron CMOS (typically 400 mW)  
Single-chip, fully integrated PHY provides PCS, PMA,  
PMD, and AUTONEG sublayers of IEEE standard  
10Base-T and 100Base-TX IEEE 802.3 compliant  
All parametric specification and timing diagrams for the  
ICS1893AF apply to the ICS1893AG. Refer to the  
ICS1893AF datasheet for detailed specifications and timing.  
Clock or crystal supported  
Media Independent Interface (MII) supported  
Managed or Unmanaged Applications  
10M or 100M Half and Full Duplex Modes  
The ICS1893AG uses the same twisted-pair transmit and  
receive circuits as the ICS1893AF, and the same  
recommended board layout techniques apply to the  
ICS1893AG.  
Auto-Negotiation with Next Page. Parallel detection for  
Legacy products  
Fully integrated, DSP-based PMD includes:  
– Adaptive equalization and baseline wander correction  
– Transmit wave shaping and stream cipher scrambler  
– MLT-3 encoder and NRZ/NRZI encoder  
The ICS1893AG is intended for Node applications using the  
standard MII interface to the MAC.  
Loopback mode for Diagnostic Functions  
Small footprint 56-pin 240 mil TSSOP package.  
ICS1893AG Block Diagram  
100Base-TX  
PCS  
PMA  
TP_PMD  
Framer  
CRS/COL  
Detection  
Parallel to Serial  
4B/5B  
Clock Recovery  
Link Monitor  
Signal Detection  
Error Detection  
MLT-3  
10/100 MII  
MAC  
Interface  
Twisted-  
Pair  
Interface to  
Magnetics  
Modulesand  
RJ45  
Interface  
MUX  
Integrated  
Switch  
Stream Cipher  
Adaptive Equalizer  
Baseline Wander  
Correction  
10Base-T  
Connector  
MII  
Low-Jitter  
Clock  
Synthesizer  
Auto-  
Negotiation  
Configuration  
and Status  
Extended  
Register  
Set  
MII  
Management  
Interface  
Clock  
Power  
LEDs and PHY  
Address  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any information  
being relied upon by the customer is current and accurate.  
ICS1893AG, Rev. A 04/14/05  
April, 2005  

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