Datasheet > ICS1893

ICS1893

更新时间： 2024-02-17 09:04:07

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
152页	968K
描述
3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩

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ICS1893 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DFN
包装说明：	HVQCCN, LCC56,.31SQ,20	针数：	56
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.31
Is Samacsys：	N	数据速率：	100000 Mbps
JESD-30 代码：	S-PQCC-N56	JESD-609代码：	e3
长度：	8 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	56
收发器数量：	1	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC56,.31SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Network Interfaces	最大压摆率：	0.16 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	INTERFACE CIRCUIT
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	8 mm	Base Number Matches：	1

ICS1893 数据手册

Integrated Circuit Systems, Inc.

Document Type: Data Sheet

Document Stage: Release

ICS1893

3.3-V 10Base-T/100Base-TX Integrated PHYceiverä

General

Features

The ICS1893 is a low-power, physical-layer device (PHY)

that supports the ISO/IEC 10Base-T and 100Base-TX

Carrier-Sense Multiple Access/Collision Detection

(CSMA/CD) Ethernet standards. The ICS1893 architecture

is based on the ICS1892. The ICS1893 supports managed

or unmanaged node, repeater, and switch applications.

• Supports category 5 cables with attenuation in excess of

24 dB at 100 MHz across a temperature range from -5° to

+85° C

• DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5° to +85° C

• Low-power, 0.35-micron CMOS (typically 400 mW)

• Single 3.3-V power supply.

The ICS1893 incorporates digital signal processing (DSP) in

its Physical Medium Dependent (PMD) sublayer. As a result,

it can transmit and receive data on unshielded twisted-pair

(UTP) category 5 cables with attenuation in excess of 24 dB

at 100 MHz. With this ICS-patented technology, the

ICS1893 can virtually eliminate errors from killer packets.

• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

• 10Base-T and 100Base-TX IEEE 802.3 compliant

• Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

The ICS1893 provides a Serial Management Interface for

exchanging command and status information with a Station

Management (STA) entity.

• Highly configurable design supports:

– Node, repeater, and switch applications

– Managed and unmanaged applications

– 10M or 100M half- and full-duplex modes

– Parallel detection

The ICS1893 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be established manually (with input pins or control

Auto-Negotiation features). W hen the ICS1893

Auto-Negotiation sublayer is enabled, it exchanges

technology capability data with its remote link partner and

automatically selects the highest-performance operating

mode they have in common.

– Auto-negotiation, with Next Page capabilities

• MAC/Repeater Interface can be configured as:

– 10M or 100M Media Independent Interface

– 100M Symbol Interface (bypasses the PCS)

– 10M 7-wire Serial Interface

• Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

ICS1893 Block Diagram

100Base-T

PCS

PMA

TP_PMD

•

Frame

CRS/COL

Detection

Parallel to Serial

4B/5B

•

Clock Recovery

Link Monitor

Signal Detection

Error Detection

•

MLT-3

10/100 MII or

Alternate

MAC/Repeater

Interface

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Interface

MUX

Integrated

Switch

Stream Cipher

Adaptive Equalizer

Baseline Wander

Correction

•

10Base-T

Connector

MII

Low-Jitter

Clock

Synthesizer

Auto-

Negotiation

Configuration

and Status

Extended

Set

MII Serial

Management

Interface

Clock

Power

LEDs and PHY

Address

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

ICS1893 Rev C 6/6/00

June, 2000

12 3 4 5 6 7...152

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与ICS1893相关器件

型号	品牌	获取价格	描述	数据表
ICS1893_09	ICSI	获取价格	3.3-V 10Base-T/100Base-TX Integrated PHYceive
ICS1893AF	ICSI	获取价格	3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893AFILF	IDT	获取价格	Interface Circuit, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
ICS1893AFLF	IDT	获取价格	3.3-V 10Base-T/100Base-TX Integrated PHYceive
ICS1893AG	ICSI	获取价格	3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI	ICSI	获取价格	3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF	ICSI	获取价格	3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGLF	ICSI	获取价格	3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893BF	ICSI	获取价格	3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893BF	IDT	获取价格	3.3-V 10Base-T/100Base-TX Integrated PHYceive

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