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ICS1890Y PDF预览

ICS1890Y

更新时间: 2024-01-13 13:17:31
品牌 Logo 应用领域
矽成 - ICSI 外围集成电路数据传输局域网
页数 文件大小 规格书
66页 1746K
描述
10Base-T/100Base-TX Integrated PHYceiver⑩

ICS1890Y 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP,
针数:64Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.79
Is Samacsys:N地址总线宽度:
边界扫描:NO数据编码/解码方法:NRZ
最大数据传输速率:12.5 MBps外部数据总线宽度:
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:14 mm低功率模式:NO
DMA 通道数量:I/O 线路数量:
串行 I/O 数:1端子数量:64
片上数据RAM宽度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedRAM(字数):0
座面最大高度:3 mm标称供电电压:5 V
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

ICS1890Y 数据手册

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ICS1890  
Integrated  
Circuit  
Systems, Inc.  
10Base-T/100Base-TX Integrated PHYceiver™  
General Description  
Features  
The ICS1890 is a fully integrated physical layer device  
supporting 10 and 100Mb/s CSMA/CD Ethernet applications.  
DTE (adapter cards or motherboards), switching hub, repeater  
and router applications are fully supported. The ICS1890  
is compliant with the ISO/IEC 8802-3 Ethernet standard  
for 10 and 100Mb/s operation.AMedia Independent Interface  
allowing direct chip-to-chip connection, motherboard-to-  
daughterboard connection or connection via an AUI-like  
cable is provided. A station management interface is  
provided to enable command information and status  
information exchange. The ICS1890 interfaces directly to  
transmit and receive isolation transformers and can support  
shielded twisted pair (STP) and unshielded twisted pair  
(UTP) category 5 cables up to 105 meters. Operation in half  
duplex or full duplex modes at either 10 or 100 Mbps  
speeds is possible with control by Auto-Negotiation or  
manual selection. By employing Auto-Negotiation the  
technology capabilities of the remote link partner may be  
determined and operation automatically adjusted to the  
highest performance common operating mode.  
•
One chip integrated physical layer  
•
•
•
•
•
All CMOS, Low power design (<200mA max)  
2
Small footprint 64-pin 14mm QFP package  
ISO/IEC 8802-3 CSMA/CD compliant  
Media Independent Interface (MII)  
Alternate 100M stream and 10M 7-wire serial  
interfaces provided  
•
•
•
10Base-TX Half & Full Duplex  
100Base-TX Half & Full Duplex  
Fully integrated TP-PMD including Stream  
Cipher Scrambler, MLT-3 encoder, Adaptive  
Equalization, and Baseline Wander Correction  
Circuitry  
Block Diagram  
PHYceiver and QuickPoll are trademarks of Integrated  
Circuit Systems, Inc. Patents pending.  
ICS1890RevG10/21/97  
ICS reserves the right to make changes in the device data identified in this publication  
without further notice. ICS advises its customers to obtain the latest version of all  
device data to verify that any information being relied upon by the customer is current  
and accurate.  

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