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ICS180MI-01T PDF预览

ICS180MI-01T

更新时间: 2024-02-16 14:31:10
品牌 Logo 应用领域
矽成 - ICSI 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
7页 101K
描述
Low EMI Clock Generator

ICS180MI-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, SOIC-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
Is Samacsys:N其他特性:ALSO OPERATES AT 5V SUPPLY
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:28 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3/5 V主时钟/晶体标称频率:28 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大压摆率:50 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS180MI-01T 数据手册

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ICS180-01  
Low EMI Clock Generator  
Description  
Features  
The ICS180-01 generates a low EMI output clock from  
a clock or crystal input. The device uses ICS’  
proprietary mix of analog and digital Phase Locked  
Loop (PLL) technology to spread the frequency  
spectrum of the output, thereby reducing the frequency  
amplitude peaks by several dB.  
Pin and function compatible to Cypress W180-01  
Packaged in 8-pin SOIC  
Provides a spread spectrum output clock  
Accepts a clock input and provides same frequency  
dithered output  
Input frequency of 8 to 28 MHz  
The ICS180-01 offers down spread selection of -1.25%  
and -3.75%. Refer to the MK1714-01/02 for the widest  
selection of input frequencies and multipliers.  
Peak reduction by 7dB - 14dB typical on 3rd - 19th  
odd harmonics  
Spread percentage selection for -1.25% and -3.75%  
Operating voltage of 3.3 V and 5 V  
ICS offers a complete line of EMI reducing clock  
generators. Consult us when you need to remove  
crystals and oscillators from your board.  
Advanced, low-power CMOS process  
Available in Pb (lead) free package  
Industrial temperature range available  
Block Diagram  
VDD  
FS2:1  
SS%  
PLL Clock  
Synthesis  
and Spread  
Spectrum  
Circuitry  
CLK  
X1/CLKIN  
Clock Buffer/  
Crystal  
Oscillator  
X2  
GND  
MDS 180-01 B  
1
Revision 050405  
Integrated Circuit Systemsl525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com  

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