Datasheet > IBMN364804CT3C-260

IBMN364804CT3C-260

更新时间： 2024-02-06 14:58:52

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
71页	1201K
描述
x8 SDRAM

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IBMN364804CT3C-260 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP54,.46,32
针数：	54	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.31	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	6 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	R-PDSO-G54
JESD-609代码：	e0	长度：	22.22 mm
内存密度：	67108864 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	8	功能数量：	1
端口数量：	1	端子数量：	54
字数：	8388608 words	字数代码：	8000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	8MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.2 mm	自我刷新：	YES
连续突发长度：	1,2,4,8,FP	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.14 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10.16 mm
Base Number Matches：	1

IBMN364804CT3C-260 数据手册

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IBMN364164 IBMN364804

IBMN364404

64Mb Synchronous DRAM - Die Revision C

Features

• Programmable Wrap: Sequential or Interleave

• Multiple Burst Read with Single Write Option

• High Performance:

-68 -75A, -260, -360,

CL=3 CL=3 CL=2 CL=3

Units

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard or Low Power operation

• 4096 refresh cycles/64ms

f_CK

t_CK

t_AC

Clock Frequency

Clock Cycle

150

133

7.5

100

100 MHz

6.67

—

Clock Access Time¹

Clock Access Time²

—

t_AC

5.4

—

1. Terminated load. See AC Characteristics on page 40.

2. Unterminated load. See AC Characteristics on page 40.

• Single Pulsed RAS Interface

• Random Column Address every CLK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by A12/A13 (Bank Select)

• Programmable CAS Latency: 2, 3

• Package: 54-pin 400 mil TSOP-Type II

• Programmable Burst Length: 1, 2, 4, 8, full-page

Description

The IBMN364404, IBMN364804, and IBMN364164

are four-bank Synchronous DRAMs organized as

4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and

1Mbit x 16 I/O x 4 Bank, respectively. These syn-

chronous devices achieve high-speed data transfer

rates of up to 150MHz by employing a pipeline chip

architecture that synchronizes the output data to a

system clock. The chip is fabricated with IBM’s

advanced 64Mbit single transistor CMOS DRAM

process technology.

accepts address data in the conventional RAS/CAS

multiplexing style. Twelve row addresses (A0-A11)

and two bank select addresses (A12, A13) are

strobed with RAS. Ten column addresses (A0-A9)

plus bank select addresses and A10 are strobed

with CAS. Column address A9 is dropped on the x8

device and column addresses A8 and A9 are

dropped on the x16 device.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A9

during a mode register set cycle. In addition, it is

possible to program a multiple burst sequence with

single write cycle for write through cache operation.

The device is designed to comply with all JEDEC

standards set for synchronous DRAM products,

both electrically and mechanically. All of the control,

address, and data input/output (I/O or DQ) circuits

are synchronized with the positive edge of an exter-

nally supplied clock.

Operating the four memory banks in an interleave

fashion allows random access operation to occur at

a higher rate than is possible with standard DRAMs.

A sequential and gapless data rate of up to 150MHz

is possible depending on burst length, CAS latency,

and speed grade of the device. Auto Refresh (CBR),

Self Refresh, and Low Power operation are sup-

ported.

RAS, CAS, WE, and CS are pulsed signals which

are examined at the positive edge of each externally

applied clock (CLK). Internal chip operating modes

are defined by combinations of these signals and a

command decoder initiates the necessary timings

for each operation. A fourteen bit address bus

19L3265.E35856B

1/01

Use is further subject to the provisions at the end of this document.

Page 1 of 71

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与IBMN364804CT3C-260相关器件

型号	品牌	获取价格	描述	数据表
IBMN364804CT3C-360	ETC	获取价格	x8 SDRAM
IBMN364804CT3C-75A	ETC	获取价格	x8 SDRAM
IBMN612404GT3B-75N	IBM	获取价格	DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612404GT3B-7N	IBM	获取价格	DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612404GT3B-8N	IBM	获取价格	DDR DRAM, 32MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612405GT3B-75N	IBM	获取价格	DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612405GT3B-7N	IBM	获取价格	DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612405GT3B-8N	IBM	获取价格	DDR DRAM, 32MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612804GT3B-75N	IBM	获取价格	DDR DRAM, 16MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMN612804GT3B-7N	IBM	获取价格	DDR DRAM, 16MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66

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