.
IBMN364164 IBMN364804
IBMN364404
64Mb Synchronous DRAM - Die Revision C
Features
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• High Performance:
-68 -75A, -260, -360,
CL=3 CL=3 CL=2 CL=3
Units
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard or Low Power operation
• 4096 refresh cycles/64ms
fCK
tCK
tAC
Clock Frequency
Clock Cycle
150
133
7.5
100
10
100 MHz
6.67
10
—
6
ns
ns
ns
Clock Access Time1
Clock Access Time2
6
—
—
6
tAC
5.4
—
1. Terminated load. See AC Characteristics on page 40.
2. Unterminated load. See AC Characteristics on page 40.
• Single Pulsed RAS Interface
• Random Column Address every CLK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by A12/A13 (Bank Select)
• Programmable CAS Latency: 2, 3
• Package: 54-pin 400 mil TSOP-Type II
• Programmable Burst Length: 1, 2, 4, 8, full-page
Description
The IBMN364404, IBMN364804, and IBMN364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. These syn-
chronous devices achieve high-speed data transfer
rates of up to 150MHz by employing a pipeline chip
architecture that synchronizes the output data to a
system clock. The chip is fabricated with IBM’s
advanced 64Mbit single transistor CMOS DRAM
process technology.
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 150MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Auto Refresh (CBR),
Self Refresh, and Low Power operation are sup-
ported.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
©IBM Corporation. All rights reserved.
19L3265.E35856B
1/01
Use is further subject to the provisions at the end of this document.
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