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IBM0436A4ANLAB-5 PDF预览

IBM0436A4ANLAB-5

更新时间: 2024-09-25 23:57:39
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
24页 440K
描述
x36 Fast Synchronous SRAM

IBM0436A4ANLAB-5 数据手册

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IBM0418A4ANLAB IBM0418A8ANLAB  
IBM0436A8ANLAB IBM0436A4ANLAB  
Preliminary 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM  
Features  
• 8Mb: 256K x 36 or 512K x 18 organizations  
4Mb: 128K x 36 or 256K x 18 organizations  
• Latched Outputs  
• Common I/O  
• 30Drivers  
• 0.25µ CMOS technology  
• Synchronous Register-Latch Mode of Operation  
with Self-Timed Late Write  
• Asynchronous Output Enable and Power Down  
Inputs  
• Single Differential PECL Clock  
• Boundary Scan using limited set of JTAG  
1149.1 functions  
• +3.3V Power Supply, Ground, 2.5V VDDQ  
• 2.5V LVTTL Input and Output levels  
• Byte Write Capability & Global Write Enable  
• Registered Addresses, Write Enables, Synchro-  
nous Select, and Data Ins  
• 7 x 17 Bump Ball Grid Array Package with  
SRAM JEDEC Standard Pinout and Boundary  
SCAN Order  
Description  
IBM0436A4ANLAB, IBM0436A8ANLAB,  
edge of the K clock, all address, write-enables, sync  
select, and data input signals are registered inter-  
nally. Data outputs are updated from output regis-  
ters off the falling edge of the K clock. An internal  
write buffer allows write data to follow one cycle  
after addresses and controls. The device is oper-  
ated with a single +3.3V power supply and is com-  
patible with 2.5V LVTTL I/O interfaces.  
IBM0418A4ANLAB, and IBM0418A8ANLAB are  
4Mb and 8Mb Synchronous Register-Latch Mode,  
high-performance CMOS Static Random Access  
Memories (SRAMs). These SRAMs are versatile,  
have a wide input/output (I/O) interface, and can  
achieve cycle times as short as 4.5ns. Differential K  
clocks are used to initiate the read/write operation;  
all internal operations are self-timed. At the rising  
crlL3325.03  
08/06/2001  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
Page 1 of 24  

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