是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
包装说明: | DIP, DIP14,.3 | Reach Compliance Code: | unknown |
风险等级: | 5.92 | Is Samacsys: | N |
JESD-30 代码: | R-PDIP-T14 | JESD-609代码: | e0 |
逻辑集成电路类型: | NAND GATE | 最大I(ol): | 0.064 A |
端子数量: | 14 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 输出特性: | OPEN-COLLECTOR |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装等效代码: | DIP14,.3 | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 电源: | 5 V |
最大电源电流(ICC): | 30 mA | Prop。Delay @ Nom-Sup: | 14.5 ns |
施密特触发器: | NO | 子类别: | Gates |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | TTL | 温度等级: | INDUSTRIAL |
端子面层: | Tin/Lead (Sn/Pb) | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
I74F50728D | NXP |
获取价格 |
Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
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I74F50728DB | ETC |
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Dual D-Type Flip-Flop |
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I74F50728D-T | ETC |
获取价格 |
Dual D-Type Flip-Flop |
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I74F50728N | NXP |
获取价格 |
Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
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I74F50728N-B | ETC |
获取价格 |
Dual D-Type Flip-Flop |
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I74F50729D | NXP |
获取价格 |
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immu |
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I74F50729DB | ETC |
获取价格 |
Dual D-Type Flip-Flop |
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I74F50729D-T | ETC |
获取价格 |
Dual D-Type Flip-Flop |
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I74F50729N | NXP |
获取价格 |
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immu |
![]() |
I74F50729N-B | ETC |
获取价格 |
Dual D-Type Flip-Flop |
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