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I0236 PDF预览

I0236

更新时间: 2023-12-20 18:44:57
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
4页 2665K
描述
Platform Manager 2 Brochure

I0236 数据手册

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INTSGRATSD POWSR, THSRꢀAꢂ AND CONTROꢂ PLNS ꢀANAGSꢀSNT  
TM  
Tꢀ  
Platform ꢀanager 2  
ꢃcalable Hardware ꢀanagement Controller  
Platform Manager 2 devices feature programmable analog with  
• Ample monitoring resources for full fault coverage  
• Accurate (0.2%) and fast (<100us) Fault detection on any channel  
• Minimized fault propagation through abundant communication between hardware  
management sub-blocks  
• Integrated power, thermal, control plane management algorithm in a single device  
FPGA on a single chip to integrate all hardware management  
(power, thermal and control plane management) functions in a  
circuit board. The Platform Manager 2 architecture uses centrally  
located hardware management algorithm within the FPGA to  
control distributed hardware management expanders (L-ASC10  
ICs) to integrate power, thermal and control plane management  
functions cost effectively from simple to complex boards  
Increases  
Reliability  
• Single design environment covers wide range of design complexities reducing design time  
• Fully verified hardware management through end-to-end simulation  
Reduces Time • Reduced design effort through correct-by-construction design methodology  
to Market  
• Distributed sense and centralized control methodology minimizes circuit board layout  
congestion  
• Fault log, software based regression test support reduces board debug time  
• Reduce BOM cost up to 50% versus multiple ICs  
• Needs fewer number of I/Os in a CPLD  
• Reduced board area and layers saves additional cost  
Lowers BOM  
and Cost  
The Platform Designer™ tool integrated in Lattice Diamond®  
software provides a single design environment to integrate a  
circuit board’s hardware management using LogiBuilder (GUI-  
based logic entry), Verilog or VHDL. The correct-by-construction  
(automatic selection, customization and wiring of IPs for a given  
design) design methodology enables seamless scaling of analog  
channels, Digital I/Os and FPGA LUTs to optimally meet specific  
hardware management requirements of a given board.  
• Simulation reduces design errors before board layout  
Reduces Risk • Re-programmability minimizes risk of board re-spins  
• Significantly reduces time-to-market  
Key Features and Benefits  
Optimized Hardware Management through Scalability  
• 10 to 80 precision voltage monitor channels  
• 3 to 24 temperature monitoring channels  
Power management functions include monitoring, supply  
sequencing, fault log, voltage scaling/VID control, trimming and  
margining functions. Thermal management includes temperature  
monitoring, fan speed control, power control and fault log. The  
control plane management includes reset distribution, I2C/SPI port  
expansion, level translation, system interface, fault logging, and  
other glue logic.  
• 60 to 384 I/Os and 640 to 9400 LUTs density  
Precision Voltage Monitoring Increases Reliability  
• Programmable threshold from 0.67V to 5.7V & 4.5V to 13.2V  
• Differential input sensing  
• Over/under voltage detection with window comparison  
• 10-bit voltage measurement ADC  
ꢀ TemperatureꢀMonitoringꢀSimplifiesꢀThermalꢀManagement  
• Measures temperature using external diode  
• Over/under temperature detection  
Temperature measurement range -60 to +150C  
High-side Current Measurement Reduces BOM  
• Measures current across shunt resistor  
• Differential range 7.5mV to 200mV  
• Common mode voltage up to 13V  
Programmable gain amplifier for current measurement  
• Fast fault detection (1µs) and over current detection  
High-Voltage FET Drivers Reduce # POLs Needed  
• Scalable from 4 to 32 N-channel MOSFET drivers  
• Digitally controlled power supply ramp control  
• Open drain output support  
Margining and Trimming for Quality Assurance  
• Scale from 4 to 32 power supplies  
• Digital closed-loop mode of operation  
• Voltage scaling and VID control  
PLD to Integrate Power, Thermal & Control Plane Functions  
• Up to 9400 LUTs and up to 384 user I/Os  
• Support for multiple interface standards  
System Level Support  
• Single 3.3V or 12V supply operation  
• Industrial temperature range  
In-System Re-programmability Reduces Risk  
On-chip configuration memory  
• JTAG/I2C programming interface and background update  
• Dual-boot recovery  
LTTICESꢀIꢁCOꢀ  

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