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I0221

更新时间: 2023-12-20 18:44:10
品牌 Logo 应用领域
莱迪思 - LATTICE 石英晶振
页数 文件大小 规格书
4页 8184K
描述
MachXO2 Product Brief

I0221 数据手册

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ThE DO-IT-ALL pLD  
MacꢀXO2 Family  
Low Cost, Low power pLD  
The MachXO2™ family of non-volatile infinitely reconfigurable  
Programmable Logic Devices (PLDs) is designed for applications  
such as telecommunications infrastructure, computing, industrial,  
medical equipment and consumer. Combining an optimized look-  
up table (LUT) architecture with 65-nm embedded Flash process  
technology, MachXO2 devices provide a flexible “do-it-all” solution  
for system designs.  
The MachXO2 family offers designers the benefits of increased  
system integration, improved system robustness and reduced  
static power consumption. In addition, the MachXO2 family  
includes hardened implementations of some of the most popular  
functions used in system applications such as User Flash Memory  
(UFM), I2C, SPI and timer/counter.  
MachXO2 devices are available in three options: high performance  
(HC, HE) and ultra-low power (ZE).  
MachXO2 Application Example  
MachXO2  
Key Features and Benefits  
Custom, I2C  
SPI, LPC  
1 2 3 4  
Large Number of Low-Cost I/Os  
Control  
µP  
Bus  
GPIO  
Up to 335 I/Os with broad range of package options  
Interface  
Robust Architecture For Reliable Operation  
Instant-on, powers up in less than 1ms  
Operate from a single 3.3/2.5/1.2V supply  
Input hysteresis allows operation in noisy environment  
Delta  
Sigma/  
PWM  
Status  
Registers  
µP  
µP  
Power  
Sequence  
& Reset  
High Functional Integration For Cost Reduction  
Densities ranging from 256 to 6864 LUTs  
Up to 240 Kbits sysMEM™ Embedded Block RAM  
Up to 54 Kbits Distributed RAM  
Up to 256 Kbits of User Flash Memory  
Hardened I2C, SPI, timer/counter functions  
Robust PLL with fractional division  
Flash  
Flash  
Controller  
I2C  
ASIC  
ASSP  
Serial  
Bus  
Bridges  
LPC  
SPI  
Flexible sysIO™ Buffer  
Three Product Options – More Flexibility  
Support for LVCMOS, LVTTL, LVDS, SSTL, HSTL interfaces  
Hot socketing  
On-chip differential termination  
Programmable pull-up or pull-down mode  
System  
Performance  
(MHz)  
Nominal  
Vcc (V)  
Internal  
Vcc (V)  
Focus  
High  
Option  
HC  
Regulator  
3.3, 2.5  
1.2  
1.2  
1.2  
1.2  
150  
150  
60  
Performance  
HE  
Pre-Engineered Source Synchronous I/O  
Dedicated gearing logic (7:1, 4:1, 8:1)  
Generic DDR, DDRX2, DDRX4  
Low Power  
ZE  
1.2  
Dedicated DDR/DDR2/LPDDR with DQS support  
3.3/2.5V  
VCC  
1.2V  
VCC  
1.2V  
VCC  
System Level Support  
VCCIO  
VCCIO  
VCCIO  
• Reliable field updates with TransFR™ and Dual Boot  
Security options include security bits, One-Time-  
Programmable (OTP) mode and unique device TraceID™  
IEEE 1532 Compliant In-System Programming  
IEEE Standard 1149.1 boundary scan  
MachXO2  
HC  
MachXO2  
HE  
MachXO2  
ZE  
Broad Device Offering  
Commercial: 0 to 85º C (TJCOM  
Industrial: -40 to 100º C (TJIND  
)
)
LATTICESEMI.COM  

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