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HY57V281620ALT-KI PDF预览

HY57V281620ALT-KI

更新时间: 2024-02-27 10:25:55
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路光电二极管ISM频段动态存储器
页数 文件大小 规格书
11页 83K
描述
4 Banks x 2M x 16bits Synchronous DRAM

HY57V281620ALT-KI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.85Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54长度:22.238 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.194 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

HY57V281620ALT-KI 数据手册

 浏览型号HY57V281620ALT-KI的Datasheet PDF文件第2页浏览型号HY57V281620ALT-KI的Datasheet PDF文件第3页浏览型号HY57V281620ALT-KI的Datasheet PDF文件第4页浏览型号HY57V281620ALT-KI的Datasheet PDF文件第5页浏览型号HY57V281620ALT-KI的Datasheet PDF文件第6页浏览型号HY57V281620ALT-KI的Datasheet PDF文件第7页 
HY57V281620A  
4 Banks x 2M x 16bits Synchronous DRAM  
DESCRIPTION  
T h e H y n i x H Y 5 7 V 2 8 1 6 2 0 A i s a 1 3 4 , 2 1 7 , 7 2 8 b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e M o b i l e a p p l i c a t i o n s w h i c h r e q u i r e  
l o w p o w e r c o n s u m p t i o n a n d e x t e n d e d t e m p e r a t u r e r a n g e . H Y 5 7 V 2 8 1 6 2 0 A i s o r g a n i z e d a s 4 b a n k s o f 2 , 0 9 7 , 1 5 2 x 1 6  
HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-  
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input a n d o u t p u t  
voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated  
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of  
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst  
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)  
FEATURES  
Single 3. 3± 0 . 3 V p o w e r s u p p l y  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m  
of pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M  
Internal four banks operation  
P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
H Y 5 7 V 2 8 1 6 2 0 A T - K I  
H Y 5 7 V 2 8 1 6 2 0 A T - H I  
H Y 5 7 V 2 8 1 6 2 0 A T - P I  
H Y 5 7 V 2 8 1 6 2 0 A T - S I  
H Y 5 7 V 2 8 1 6 2 0 A L T - K I  
H Y 5 7 V 2 8 1 6 2 0 A L T - H I  
H Y 5 7 V 2 8 1 6 2 0 A L T - P I  
H Y 5 7 V 2 8 1 6 2 0 A L T - S I  
1 3 3 M H z  
1 3 3 M H z  
1 0 0 M H z  
1 0 0 M H z  
1 3 3 M H z  
1 3 3 M H z  
1 0 0 M H z  
1 0 0 M H z  
N o r m a l  
4 B a n k s x 2 M b i t s  
x 1 6  
L V T T L  
4 0 0 m i l 5 4 p i n T S O P I I  
L o w P o w e r  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of  
circuits described. No patent licenses are implied.  
R e v . 0 . 4 / A p r . 0 1  

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