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HYMP112S64M8-E3 PDF预览

HYMP112S64M8-E3

更新时间: 2024-02-09 08:12:29
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器双倍数据速率
页数 文件大小 规格书
23页 769K
描述
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.

HYMP112S64M8-E3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.92访问模式:DUAL BANK PAGE BURST
最长访问时间:0.6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:R-XZMA-N200内存密度:8589934592 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:200字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:55 °C最低工作温度:
组织:128MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM200,24封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.08 A子类别:DRAMs
最大压摆率:2.2 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.6 mm端子位置:ZIG-ZAG
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

HYMP112S64M8-E3 数据手册

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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.  
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2  
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based  
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-  
try standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate2 Synchronous  
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power  
Supply  
Programmable Burst Length 4 / 8 with both sequen-  
tial and interleave mode  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
All inputs and outputs are compatible with SSTL_1.8  
interface  
Serial presence detect with EEPROM  
Posted CAS  
DDR2 SDRAM Package: 60ball(x8), 84ball(x16)  
FBGA  
Programmable CAS Latency 3 ,4 ,5  
OCD (Off-Chip Driver Impedance Adjustment) and  
ODT (On-Die Termination)  
67.60 x 30.00 mm form factor  
Lead-free Products are RoHS compliant  
Fully differential clock operations (CK & CK)  
ORDERING INFORMATION  
# of  
DRAMs  
# of  
ranks  
Part Name  
Density  
Organization  
Materials  
HYMP532S646-E3/C4  
HYMP564S648-E3/C4  
HYMP564S646-E3/C4  
HYMP112S64M8-E3/C4  
HYMP532S64P6-E3/C4  
HYMP564S64P8-E3/C4  
HYMP564S64P6-E3/C4  
HYMP112S64MP8-E3/C4  
256MB  
512MB  
512MB  
1GB  
32Mx64  
64Mx64  
64Mx64  
128Mx64  
32Mx64  
64Mx64  
64Mx64  
128Mx64  
4
8
1
1
2
2
1
1
2
2
Leaded  
Leaded  
8
Leaded  
16  
4
Leaded  
256MB  
512MB  
512MB  
1GB  
Lead free  
Lead free  
Lead free  
Lead free  
8
8
16  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.0 / Feb. 2005  
1

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