Datasheet > HY5V22F-55I

HY5V22F-55I

更新时间： 2024-11-28 07:33:07

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
14页	292K
描述
Synchronous DRAM, 4MX32, 5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90

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HY5V22F-55I 数据手册

HY57V283220T-I/ HY5V22F-I

4 Banks x 1M x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V283220T-I / HY5V22F-I is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the mem-

ory applications which require wide data I/O and high bandwidth. HY57V283220T-I / HY5V22F-I is organized as

4banks of 1,048,576x32.

HY57V283220T-I / HY5V22F-I is offering fully synchronous operation referenced to a positive edge of the clock. All

inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to

achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V283220(L)T-5I

HY5V22(L)F-5I

4Banks x 1Mbits

x32

86TSOP-II

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

LVTTL

90Ball FBGA

HY57V283220(L)T-55I

HY5V22(L)F-55I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

LVTTL

HY57V283220(L)T-6I

HY5V22(L)F-6I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-7I

HY5V22(L)F-7I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-8I

HY5V22(L)F-8I

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-PI

HY5V22(L)F-PI

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

HY57V283220(L)T-SI

HY5V22(L)F-SI

4Banks x 1Mbits

x32

86TSOP-II

90Ball FBGA

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.6/Nov. 02

12 3 4 5 6 7...14

中文翻译

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与HY5V22F-55I相关器件

型号	品牌	获取价格	描述	数据表
HY5V22F-5I	HYNIX	获取价格	Synchronous DRAM, 4MX32, 4.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22F-6	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22F-6I	HYNIX	获取价格	Synchronous DRAM, 4MX32, 5.5ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22F-7	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22F-8	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22F-8I	HYNIX	获取价格	Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90
HY5V22F-H	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22F-P	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22FP-5	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22FP-55	HYNIX	获取价格	4 Banks x 1M x 32Bit Synchronous DRAM

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