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HY5R144HM745 PDF预览

HY5R144HM745

更新时间： 2024-09-17 19:28:43
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器内存集成电路
页数 文件大小 规格书
63页 3849K
描述
Rambus DRAM, 8MX18, 45ns, CMOS, PBGA62, MICRO, BGA-62

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中文翻译

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HY5R144HM745 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VBGA,针数：62
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.24风险等级：5.84
访问模式：BLOCK ORIENTED PROTOCOL最长访问时间：45 ns
其他特性：SELF CONTAINED REFRESHJESD-30 代码：R-PBGA-B62
JESD-609代码：e1长度：12.3 mm
内存密度：150994944 bit内存集成电路类型：RAMBUS DRAM
内存宽度：18功能数量：1
端口数量：1端子数量：62
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS组织：8MX18
封装主体材料：PLASTIC/EPOXY封装代码：VBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE
认证状态：Not Qualified座面最大高度：0.91 mm
自我刷新：YES最大供电电压 (Vsup)：2.63 V
最小供电电压 (Vsup)：2.37 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：11.8 mmBase Number Matches：1

HY5R144HM745 数据手册

 浏览型号HY5R144HM745的Datasheet PDF文件第2页浏览型号HY5R144HM745的Datasheet PDF文件第3页浏览型号HY5R144HM745的Datasheet PDF文件第4页浏览型号HY5R144HM745的Datasheet PDF文件第5页浏览型号HY5R144HM745的Datasheet PDF文件第6页浏览型号HY5R144HM745的Datasheet PDF文件第7页 
Direct RDRAM™  
128/144Mbit (256Kx16/18x32s) Preliminary  
Overview  
The Rambus Direct RDRAM™ is a general purpose high-  
performance memory device suitable for use in a broad  
range of applications including computer memory, graphics,  
video, and any other application where high bandwidth and  
low latency are required.  
The 128/144-Mbit Direct Rambus DRAMs (RDRAMâ ) are  
extremely high-speed CMOS DRAMs organized as 8M  
words by 16 or 18 bits. The use of Rambus Signaling Level  
(RSL) technology permits 600MHz to 800MHz transfer  
rates while using conventional system and board design  
technologies. Direct RDRAM devices are capable of  
sustained data transfers at 1.25 ns per two bytes (10ns per  
sixteen bytes).  
The architecture of the Direct RDRAMs allows the highest  
sustained bandwidth for multiple, simultaneous randomly  
addressed memory transactions. The separate control and  
data buses with independent row and column control yield  
over 95% bus efficiency. The Direct RDRAM's 32 banks  
support up to four simultaneous transactions.  
Figure 1: Direct RDRAM uBGA Package  
The 128/144-Mbit Direct RDRAMs are offered in a uBGA  
package suitable for desktop as well as low-profile add-in  
card and mobile applications.  
System oriented features for mobile, graphics and large  
memory systems include power management, byte masking,  
and x18 organization. The two data bits in the x18 organiza-  
tion are general and can be used for additional storage and  
bandwidth or for error correction.  
Direct RDRAMs operate from a 2.5 volt supply.  
Key Timing Parameters/Part Numbers  
Features  
I/O Freq. Core Access Time  
Part  
Number  
Organizationa  
MHz  
(ns)  
· Highest sustained bandwidth per DRAM device  
- 1.6GB/s sustained data transfer rate  
- Separate control and data buses for maximized  
efficiency  
256Kx16x32s  
256Kx16x32s  
256Kx16x32s  
256Kx16x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
256Kx18x32s  
600  
711  
800  
800  
600  
711  
800  
800  
600  
711  
800  
800  
53  
45  
45  
40  
53  
45  
45  
40  
53  
45  
45  
40  
HY5R128HC653  
HY5R128HC745  
HY5R128HC845  
HY5R128HC840  
HY5R144HC653  
HY5R144HC745  
HY5R144HC845  
HY5R144HC840  
HY5R144HMb653  
HY5R144HM745  
HY5R144HM845  
HY5R144HM840  
- Separate row and column control buses for  
easy scheduling and highest performance  
- 32 banks: four transactions can take place simul-  
taneously at full bandwidth data rates  
· Low latency features  
- Write buffer to reduce read latency  
- 3 precharge mechanisms for controller flexibility  
- Interleaved transactions  
· Advanced power management:  
- Multiple low power states allows flexibility in  
power consumption versus time to transition to active  
state  
a. The “ 32s” designation indicates that this RDRAM core is com-  
posed of 32 banks which use a “split” bank architecture.  
b. The “ M” indicates the mirrored package.  
- Power-down self-refresh  
· Organization: 1Kbyte pages and 32 banks, x 16/18  
- x18 organization allows ECC configurations or  
increased storage/bandwidth  
- x16 organization for low cost applications  
· Uses Rambus Signaling Level (RSL) for up to  
800MHz operation  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.1/June.00  
1
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