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HY57V561620LT-SI PDF预览

HY57V561620LT-SI

更新时间: 2024-11-05 23:57:11
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
11页 64K
描述
x16 SDRAM

HY57V561620LT-SI 数据手册

 浏览型号HY57V561620LT-SI的Datasheet PDF文件第2页浏览型号HY57V561620LT-SI的Datasheet PDF文件第3页浏览型号HY57V561620LT-SI的Datasheet PDF文件第4页浏览型号HY57V561620LT-SI的Datasheet PDF文件第5页浏览型号HY57V561620LT-SI的Datasheet PDF文件第6页浏览型号HY57V561620LT-SI的Datasheet PDF文件第7页 
HY57V561620T  
4Banks x 4M x 16Bit Synchronous DRAM  
DESCRIPTION  
T h e H y n i x H Y 5 7 V 5 6 1 6 2 0 i s  
a
2 6 8 , 4 3 5 , 4 5 6 b i t C M O S S y n c h r o n o u s D R A M , i d e a l l y s u i t e d f o r t h e M o b i l e a p p l i c a t i o n s  
w h i c h r e q u i r e l o w p o w e r c o n s u m p t i o n a n d e x t e n d e d t e m p e r a t u r e r a n g e . H Y 5 7 V 5 6 1 6 2 0 i s o r g a n i z e d a s  
4, 194, 304x16.  
4 b a n k s o f  
HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs  
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high  
bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline ( C A S latency of 2 or 3), the number of consecutive read or write  
cycles initiated by  
a
single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y  
design is not restricted by a `2N` rule.)  
a n e w b u r s t r e a d o r w r i t e c o m m a n d o n a n y c y c l e . ( T h i s p i p e l i n e d  
FEATURES  
S i n g l e 3 . 3 V ± 0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
8 1 9 2 r e f r e s h c y c l e s / 6 4 m s  
J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m  
of pin pitch  
P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e  
- 1, 2, 4, 8 and Full Page for Sequential Burst  
- 1, 2, 4 and 8 for Interleave Burst  
P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks  
All inputs and outputs referenced to positive edge of  
system clock  
D a t a m a s k f u n c t i o n b y U D Q M a n d L D Q M  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
H Y 5 7 V 5 6 1 6 2 0 T - H I  
H Y 5 7 V 5 6 1 6 2 0 T - S I  
H Y 5 7 V 5 6 1 6 2 0 L T - H I  
H Y 5 7 V 5 6 1 6 2 0 L T - S I  
1 3 3 M H z  
1 0 0 M H z  
1 3 3 M H z  
1 0 0 M H z  
N o r m a l  
P o w e r  
4Banks x 4Mbits  
x 1 6  
L V T T L  
400mil 54pin TSOP II  
L o w P o w e r  
This document is  
a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Revision 0. 1/ Apr. 01  

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