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HY29F400ATG-90 PDF预览

HY29F400ATG-90

更新时间： 2024-11-06 04:44:03
品牌 Logo 应用领域
海力士 - HYNIX 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
40页 591K
描述
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory

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中文翻译

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HY29F400ATG-90 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SOP-44针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.77
Is Samacsys：N最长访问时间：90 ns
备用内存宽度：8启动块：TOP
命令用户界面：YES数据轮询：YES
耐久性：100000 Write/Erase CyclesJESD-30 代码：R-PDSO-G44
长度：28.2 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：16
功能数量：1部门数/规模：1,2,1,7
端子数量：44字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX16封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP44,.63
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL电源：5 V
编程电压：5 V认证状态：Not Qualified
就绪/忙碌：YES座面最大高度：2.8 mm
部门规模：16K,8K,32K,64K最大待机电流：0.001 A
子类别：Flash Memories最大压摆率：0.06 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL切换位：YES
类型：NOR TYPE宽度：13.3 mm
Base Number Matches：1

HY29F400ATG-90 数据手册

 浏览型号HY29F400ATG-90的Datasheet PDF文件第2页浏览型号HY29F400ATG-90的Datasheet PDF文件第3页浏览型号HY29F400ATG-90的Datasheet PDF文件第4页浏览型号HY29F400ATG-90的Datasheet PDF文件第5页浏览型号HY29F400ATG-90的Datasheet PDF文件第6页浏览型号HY29F400ATG-90的Datasheet PDF文件第7页 
HY29F400A  
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory  
KEY FEATURES  
ꢀ 5 Volt Read, Program, and Erase  
– Minimizes system-level power requirements  
ꢀ High Performance  
– Access times as fast as 50 ns  
ꢀ Low Power Consumption  
– 20 mA typical active read current in byte  
mode, 28 mA typical in word mode  
– 30 mA typical program/erase current  
– 5 µA maximum CMOS standby current  
ꢀ Compatible with JEDEC Standards  
– Package, pinout and command-set  
compatible with the single-supply Flash  
device standard  
ꢀ Sector Protection  
– Any combination of sectors may be locked  
to prevent program or erase operations  
within those sectors  
ꢀ Temporary Sector Unprotect  
– Allows changes in locked sectors  
(requires high voltage on RESET# pin)  
ꢀ Internal Erase Algorithm  
– Automatically erases a sector, any  
combination of sectors, or the entire chip  
ꢀ Internal Programming Algorithm  
– Automatically programs and verifies data  
at a specified address  
– Provides superior inadvertent write  
protection  
ꢀ Fast Program and Erase Times  
– Byte programming time: 7 µs typical  
– Sector erase time: 1.0 sec typical  
– Chip erase time: 11 sec typical  
ꢀ Data# Polling and Toggle Status Bits  
– Provide software confirmation of  
completion of program or erase  
operations  
ꢀ Ready/Busy# Output (RY/BY#)  
– Provides hardware confirmation of  
completion of program and erase  
operations  
ꢀ Sector Erase Architecture  
– Boot sector architecture with top and  
bottom boot block options available  
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte  
and seven 64 Kbyte sectors in byte mode  
– One 8 Kword, two 4 Kword, one 16 Kword  
and seven 32 Kword sectors in word mode  
– A command can erase any combination of  
sectors  
– Supports full chip erase  
ꢀ Erase Suspend/Resume  
ꢀ 100,000 Program/Erase Cycles Minimum  
ꢀ Space Efficient Packaging  
– Available in industry-standard 44-pin  
PSOP and 48-pin TSOP and reverse  
TSOP packages  
– Temporarily suspends a sector erase  
operation to allow data to be read from, or  
programmed into, any sector not being  
erased  
GENERAL DESCRIPTION  
LOGIC DIAGRAM  
The HY29F400A is a 4 Megabit, 5 volt only CMOS  
Flash memory organized as 524,288 (512K) bytes  
or 262,144 (256K) words. The device is offered in  
industry-standard 44-pin PSOP and 48-pin TSOP  
packages.  
18  
8
7
A[17:0]  
CE#  
DQ[7:0]  
DQ[14:8]  
The HY29F400A can be programmed and erased  
in-system with a single 5-volt VCC supply. Internally  
generated and regulated voltages are provided for  
program and erase operations, so that the device  
does not require a high voltage power supply to  
perform those functions. The device can also be  
programmed in standard EPROM programmers.  
Access times as fast as 55 ns over the full operat-  
ing voltage range of 5.0 volts ± 10% are offered  
for timing compatibility with the zero wait state re-  
quirements of high speed microprocessors. A 55  
ns version operating over 5.0 volts ± 5% is also  
OE#  
DQ[15]/A-1  
WE#  
RESET#  
BYTE#  
RY/BY#  
Preliminary  
Revision 1.0, January 2002  
1234567...40

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