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HY29DL162TF-70I PDF预览

HY29DL162TF-70I

更新时间: 2024-02-08 13:24:26
品牌 Logo 应用领域
海力士 - HYNIX 闪存存储内存集成电路
页数 文件大小 规格书
48页 548K
描述
16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162TF-70I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:8 X 9 MM, FBGA-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.89Is Samacsys:N
最长访问时间:70 ns备用内存宽度:8
启动块:TOP命令用户界面:YES
通用闪存接口:YES数据轮询:YES
JESD-30 代码:R-PBGA-B48JESD-609代码:e0
长度:9 mm内存密度:16777216 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1部门数/规模:8,31
端子数量:48字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA48,6X8,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/3.3 V编程电压:3 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:1.2 mm部门规模:8K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.045 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:YES类型:NOR TYPE
宽度:8 mmBase Number Matches:1

HY29DL162TF-70I 数据手册

 浏览型号HY29DL162TF-70I的Datasheet PDF文件第2页浏览型号HY29DL162TF-70I的Datasheet PDF文件第3页浏览型号HY29DL162TF-70I的Datasheet PDF文件第4页浏览型号HY29DL162TF-70I的Datasheet PDF文件第5页浏览型号HY29DL162TF-70I的Datasheet PDF文件第6页浏览型号HY29DL162TF-70I的Datasheet PDF文件第7页 
HY29DL162/HY29DL163  
16 Megabit (2M x 8/1M x16) Low Voltage,  
Dual Bank, Simultaneous Read/Write Flash Memory  
KEY FEATURES  
n Data# Polling and Toggle Bits  
n Single Power Supply Operation  
Read, program, and erase operations  
from 2.7 to 3.6 V  
Provide software confirmation of completion  
of program or erase operations  
n Ready/Busy# Pin  
Ideal for battery-powered applications  
n Simultaneous Read/Write Operations  
Host system can program or erase in one  
bank while simultaneously reading from any  
sector in the other bank with zero latency  
between read and write operations  
n High Performance  
Provides hardware confirmation of  
completion of program or erase operations  
n Erase Suspend  
Suspends an erase operation to allow  
programming data to or reading data from  
a sector in the same bank  
Erase Resume can then be invoked to  
complete the suspended erasure  
n Hardware Reset Pin (RESET#) Resets the  
Device to Reading Array Data  
70 and 80 ns access time versions with  
30pF load  
90 and 120 ns access time versions with  
100pF load  
n WP#/ACC Input Pin  
n Ultra Low Power Consumption (Typical  
Values)  
Write protect (WP#) function allows  
hardware protection of two outermost boot  
sectors, regardless of sector protect status  
Acceleration (ACC) function provides  
accelerated program times  
Automatic sleep mode current: 200 nA  
Standby mode current: 200 nA  
Read current: 10 mA (at 5 MHz)  
Program/erase current: 15 mA  
n Boot-Block Sector Architecture with 39  
Sectors in Two Banks for Fast In-System  
Code Changes  
n Fast Program and Erase Times  
Sector erase time: 0.5 sec typical  
Byte/Word program time utilizing  
Acceleration function: 10 µs typical  
n Space Efficient Packaging  
n Secured Sector: An Extra 64 Kbyte Sector  
that Can Be:  
48-pin TSOP and 48-ball FBGA packages  
Factory locked and identifiable: 16 bytes  
available for a secure, random factory-  
programmed Electronic Serial Number  
Customer lockable: Can be read, program-  
med, or erased just like other sectors  
n Flexible Sector Architecture  
Sector Protection allows locking of a  
sector or sectors to prevent program or  
erase operations within that sector  
Temporary Sector Unprotect allows  
changes in locked sectors (requires high  
voltage on RESET# pin)  
n Automatic Erase Algorithm Erases Any  
Combination of Sectors or the Entire Chip  
n Automatic Program Algorithm Writes and  
Verifies Data at Specified Addresses  
n Compliant with Common Flash Memory  
Interface (CFI) Specification  
LOGIC DIAGRAM  
20  
8
7
A[19:0]  
CE#  
DQ[7:0]  
DQ[14:8]  
DQ[15]/A[-1]  
WP#/ACC  
RY/BY#  
OE#  
W E#  
RESET#  
BYTE#  
n Minimum 100,000 Write Cycles per Sector  
(1,000,000 cycles Typical)  
n Compatible with JEDEC Standards  
Pinout and software compatible with  
single-power supply Flash devices  
Superior inadvertent write protection  
Preliminary  
Revision 1.3, June 2001  

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