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HV6810PJ-GM910 PDF预览

HV6810PJ-GM910

更新时间: 2024-01-09 06:18:49
品牌 Logo 应用领域
超科 - SUPERTEX 驱动接口集成电路
页数 文件大小 规格书
9页 844K
描述
Vacuum Fluorescent Driver

HV6810PJ-GM910 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.69接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVER
JESD-609代码:e3峰值回流温度(摄氏度):NOT SPECIFIED
端子面层:MATTE TIN处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

HV6810PJ-GM910 数据手册

 浏览型号HV6810PJ-GM910的Datasheet PDF文件第2页浏览型号HV6810PJ-GM910的Datasheet PDF文件第3页浏览型号HV6810PJ-GM910的Datasheet PDF文件第4页浏览型号HV6810PJ-GM910的Datasheet PDF文件第5页浏览型号HV6810PJ-GM910的Datasheet PDF文件第6页浏览型号HV6810PJ-GM910的Datasheet PDF文件第7页 
HV6810  
Supertex inc.  
10-Channel, Serial-Input  
Latched Display Driver  
Features  
General Description  
High output voltage 80V  
The HV6810 is a monolithic integrated circuit designed  
to drive a dot matrix or segmented vacuum fluorescent  
display (VFD). These devices feature a serial data output to  
cascade additional devices for large displays.  
High speed 5MHz @5.0VDD  
Low power IBB ≤ 0.1mA (all high)  
Active pull down 100µA min @25OC  
Output source current 25mA @60V VBB  
Each device drives 10 lines  
High-speed serially-shifted data input  
5.0V CMOS-compatible inputs  
Latches on all driver outputs  
A 10-bit data word is serially loaded into the shift register  
on the positive-going transition of the clock. Parallel data  
is transferred to the output buffers through a 10-bit D-type  
latch while the latch enable input is high, and is latched  
when the latch enable is low. When the blanking input is  
high, all of the outputs are low.  
Pin-compatible replacement for UCN5810A and  
TL4810A, TL4810B  
Outputs are structures formed by double-diffused MOS  
(DMOS) transistors with output voltage ratings of 80V and  
25mA source-current capability. All inputs are compatible  
with CMOS levels.  
Applications  
High speed dot matrix print head driver  
VFD (vacuum fluorescent display) driver  
Functional Block Diagram  
VBB  
Blanking  
Latch Enable  
Shift Register  
Latches  
Data Input  
Clock  
1D  
C1  
C2  
2D  
LC1  
LC2  
Q1  
Q2  
1D  
C1  
C2  
2D  
6 Stages  
(Q3 thru Q8  
not shown  
C2  
2D  
1D  
C1  
LC9  
Q9  
1D  
C1  
C2  
2D  
LC10  
Q10  
Serial  
Out  
Logic Diagram (positive logic)  
Doc.# DSFP-HV6810  
D071012  
Supertex inc.  
www.supertex.com  

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