HS3120C-2Q

更新时间： 2024-11-24 13:08:23

品牌	Logo	应用领域
APITECH		转换器数模转换器
页数	文件大小	规格书
3页	3671K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, 2us Settling Time, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28

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技术参数
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HS3120C-2Q 技术参数

生命周期：	Active	包装说明：	DIP,
Reach Compliance Code：	compliant	风险等级：	5.69
转换器类型：	D/A CONVERTER	输入位码：	BINARY, OFFSET BINARY, COMPLEMENTARY BINARY
输入格式：	PARALLEL, WORD	JESD-30 代码：	R-CDIP-T28
长度：	35.555 mm	最大线性误差 (EL)：	0.015%
位数：	12	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称安定时间 (tstl)：	2 µs
标称供电电压：	15 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
Base Number Matches：	1

HS3120C-2Q 数据手册

HS 3120

Data Converter Line

Double Buffered 12-Bit MDAC

FEATURES

• M onolithic Construction

• 12-Bit Resolution

• 0.01% Non-Linearity

• jup Compatible

• 4-Quadrant M ultiplication

• Latch-up Protected

DESCRIPTION

The HS 3120 is a precision monolithic 12-bit

multiplying DAC with internal two-stage input

storage registers for easy interfacing with

microprocessor busses. It is packaged in a 28-pin DIP

to give high I/O design flexibility.

controls are level-triggered to allow static or dynamic

operation.

DOUBLE BUFFERED —The input registers are sectioned

into 3 segments of 4 bits each, all individually

addressable. The DAC register, following the input

registers, is a parallel 12-bit register for holding the

DAC data while the input registers are updated. Only

the data held in the DAC register determines the

analog output value of the converter.

VERSATILE OUTPUTS —A total of 5 output lines are

provided by the HS 3120 to allow unipolar and

bipolar output connection with a minimum of

external components. The feedback resistor is

internal. The resistor ladder network termination is

externally available, thus eliminating an external

resistor for the 1 LSB offset in bipolar mode.

M ICRO PROCESSOR COM PATIBLE — The HS 3120 has

been designed for great flexibility in connecting to

bus-oriented systems. The 12 data inputs are

organized into 3 independent addressable 4-bit input

registers such that the HS 3120 can be connected to

either a 4, 8 or 16-bit data bus. The control logic of

the HS 3120 includes chip enable and latch enable

inputs for flexible memory mapping. All

M ONOLITHIC CM OS CONSTRUCTION —The HS 3120

is a one-chip CM OS circuit with a resistor ladder

network designed for 0.01% linearity without laser

trimming. Small chip size and high manufacturing

yields result in greatly reduced cost.

FUNCTIONAL DIAGRAM

(M SB)

(LSB)

10 11 BIT 12

BIT

REF

10 11 12

13 14 15 16

17 18 19 20

INPUT REGISTER

HBE

INPUT REGISTER

CONTROL

LOGIC

M BE

LBE

LDAC

DAC REGISTER

12 BIT M DAC

HS 3120

GND

LDTR

GND

DD1

DD2

165CedarHill Street,Marlborough,MA01752 Tel:508.485.6350 Fax: 508.485.5168

www.SpectrumMicrowave.com

12 3

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