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HRF-AT4521-AU-TR

更新时间： 2024-11-20 13:00:11
品牌 Logo 应用领域
霍尼韦尔 - HONEYWELL 衰减器
页数 文件大小 规格书
8页 92K
描述
Analog Circuit,

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中文翻译

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HRF-AT4521-AU-TR 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：NBase Number Matches：1

HRF-AT4521-AU-TR 数据手册

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HRF-AT4521  
Preliminary  
31.0 dB, DC-4GHz, 5 Bit  
Serial Digital Attenuator  
Features  
•
•
•
•
•
•
Very Low DC Power Consumption  
Attenuation In Steps From 1 dB To 31 dB  
Single Or Dual Power Supply Voltages  
Serial Data Interface  
50 Ohm Compatible Impedance  
Space Saving LPCCTM Surface Mount Packaging  
Product Description  
The Honeywell HRF-AT4521 is  
a
5-bit digital  
attenuator that is ideal for use in broadband  
communication system applications that require  
accuracy, speed and low power consumption. The  
HRF-AT4521 is manufactured with Honeywell's  
patented Silicon On Insulator (SOI) CMOS  
HRF-AT4521 in LPCC™ Package  
manufacturing  
technology, which provides the  
performance of GaAs with the economy and  
integration capabilities of conventional CMOS.  
RF Electrical Specifications @ + 25oC  
Parameter  
Test Condition  
Frequency  
Minimum  
Typical  
Maximum  
Units  
dB  
dB  
Insertion Loss  
DC – 0.5 GHz  
2.0 GHz  
1.8  
2.8  
--  
3.0 GHz  
dB  
4.0 GHz  
--  
dB  
1dB Compression  
1dB Compression  
Input IP3  
VSS = 0V, Input Power  
DC – 2.0 GHz  
24  
dBm  
VSS = - VDD, Input Power  
DC – 2.0 GHz  
DC – 2.0 GHz  
29  
38  
dBm  
dBm  
VSS = 0V Two-tone inputs  
Up To +5 dBm @ 0 dBm  
Attenuation  
Input IP3  
Vss = - VDD  
DC – 2.0 GHz  
>38  
11  
dBm  
Two-tone inputs Up To + 5  
dBm @ 0 dBm Attenuation  
Any Combination of Bits  
All attenuation states  
All attenuation states  
All attenuation states  
All attenuation states  
10% To 90%  
50% Cntl To 90%/10%RF  
In-Band  
T high / T low = ½ minimum clock period  
Set up to rising edge of clock  
Return Loss*  
Attenuation Accuracy  
DC - 4.0 GHz  
DC – 1.0 GHz  
2.0 GHz  
dB  
dB  
dB  
dB  
dB  
nS  
nS  
mV  
nS  
nS  
nS  
nS  
+/-(0.3 + 3% of programmed IL)  
+/-(0.3 + 3% of programmed IL)  
+/-(0.4 + 4% of programmed IL)  
+/-(0.5 + 6% of programmed IL)  
TBD  
3.0 GHz  
4.0 GHz  
Trise, Tfall*  
Ton, Toff (Tpd)  
Transients  
T clock Period (Tprd)*  
T data set up (Tsup)*  
T data hold (Thld)*  
T latch set up (Tlsup)*  
50  
5
2
Data hold after rising edge of clock  
Data set up to falling edge of OE  
5
0.01uF Decoupling Capacitors Required On Power Supply Rails.  
________________________________________________________________________________________________________  
*By design  
Web Site:  
Email:  
www.mysoiservices.com  
mysoiservices@honeywell.com  
Honeywell  
Solid State Electronics Center  
12001 State Highway 55  
2002 4521W  
Published June 2002 Page 1  
Plymouth, Minnesota 55441-4799  
1-800-323-8295  
12345678

中文翻译

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