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HMC698LP5ETR

更新时间： 2024-11-23 13:08:23
品牌 Logo 应用领域
HITTITE ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
12页 694K
描述
Support Circuit, 1-Func, PQCC32, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, SMT-32

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HMC698LP5ETR 技术参数

生命周期：Transferred包装说明：VQCCN,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.79JESD-30 代码：S-PQCC-N32
长度：5 mm功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE座面最大高度：1 mm
标称供电电压：5 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：5 mm
Base Number Matches：1

HMC698LP5ETR 数据手册

 浏览型号HMC698LP5ETR的Datasheet PDF文件第2页浏览型号HMC698LP5ETR的Datasheet PDF文件第3页浏览型号HMC698LP5ETR的Datasheet PDF文件第4页浏览型号HMC698LP5ETR的Datasheet PDF文件第5页浏览型号HMC698LP5ETR的Datasheet PDF文件第6页浏览型号HMC698LP5ETR的Datasheet PDF文件第7页 
HMC698LP5 / 698LP5E  
v03.0709  
7 GHz INTEGER N SYNTHESIZER  
(N = 12 - 259)  
Typical Applications  
Features  
Ultra Low SSB Phase Noise Floor:  
-153 dBc/Hz @ 10 kHz offset @ 100 MHz  
Reference Frequency.  
The HMC698LP5(E) is ideal for:  
• Satellite Communication Systems  
• Point-to-Point Radios  
Programmable Divider (N= 12 - 259) Operating  
up to 7 GHz  
• Military Applications  
• Sonet Clock Generation  
Open Collector Output Buffer Amplifiers for  
Interfacing w/ Op-Amp Based Loop Filter  
Reversible Polarity PFD w/ Lock Detect Output  
32 Lead 5x5mm SMT Package: 25mm2  
Functional Diagram  
General Description  
The HMC698LP5(E) is a frequency synthesizer with  
a wideband reversible polarity digital PFD and lock  
detect output. The divider operates unconditionally  
from 80 - 7000 MHz with a continuous integer division  
ratio of 12 to 259. The HMC698LP5(E) high frequency  
operation along with ultra low phase noise floor make  
possible synthesizers with wide loop bandwidth and  
low N resulting in fast settling and very low phase  
noise. When used in conjunction with a differential  
loop filter, the HMC698LP5(E) can be used to phase  
lock a VCO to a reference oscillator.  
11  
Electrical Specifications, TA = +25° C, Vcc = Vcc1 = Vcc2 = Vcc3 = Vcc_pd = 5V  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Units  
MHz  
MHz  
dBm  
MHz  
MHz  
dBm  
Maximum Ref. Input Frequency  
Minimum Ref. Input Frequency  
Reference Input Power Range  
Maximum VCO Input Frequency  
Minimum VCO Input Frequency  
VCO Input Power Range  
Sine or Square Wave Input [1]  
Square Wave Input [2]  
100 MHz Frequency  
1300  
10  
+5  
-5  
7000  
80  
+5  
100 MHz Input Frequency  
Gain = Vpp / 2π Rad.  
-10  
PFD Output Voltage  
PFD Gain  
2000  
0.32  
mV, Pk - Pk  
V/Rad.  
@ 10 kHz Offset @ 100 MHz Square Wave Ref. Input  
Pin= 0 dBm  
SSB Phase Noise  
-153  
310  
dBc/Hz  
mA  
Total Supply Current  
[1] Maximum frequencies may be limited by available counter division ratio.  
[2] Square wave input achieves best phase noise at lower ref. frequency (see sine & square wave comparison plots)  
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:  
20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373  
Order On-line at www.hittite.com  
11 - 12  
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