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1-8
HIP6501A
FN4749
Rev 6.00
December 30, 2004
Triple Linear Power Controller with ACPI Control Interface
The HIP6501A, paired with either the HIP6020 or HIP6021,
simplifies the implementation of ACPI-compliant designs in
microprocessor and computer applications. The IC
integrates two linear controllers and a low-current pass
transistor, as well as the monitoring and control functions
into a 16-pin SOIC package. One linear controller generates
Features
• Provides 3 ACPI-Controlled Voltages
- 5V Active/Sleep (5V
)
DUAL
- 3.3V Active/Sleep (3.3V
)
DUAL
- 2.5V/3.3V Active/Sleep (2.5V
)
MEM
the 3.3V
voltage plane from an ATX power supply’s
• Simple Control Design - No Compensation Required
• Excellent Output Voltage Regulation
DUAL
5VSB output during sleep states (S3, S4/S5), powering the
PCI slots through an external pass transistor, as instructed
by the status of the 3.3V
- 3.3V
DUAL
Output: 2.0% Over Temperature; Sleep
enable pin. An additional pass
DUAL
States Only
transistor is used to switch in the ATX 3.3V output for PCI
operation during S0 and S1 (active) operatingstates. The
second linear controller supplies the computer system’s
2.5V/3.3V memory power through an external pass
transistor in active states. During S3 state, an integrated
pass transistor supplies the 2.5V/3.3V sleep-state power. A
- 2.5V/3.3V Output: 2.0% Over Temperature; Both
Operational States (3.3V setting in sleep only)
• Fixed Output Voltages Require No Precision External
Resistors
• Small Size
- Small External Component Count
third controller powers up a 5V
plane by switching in
DUAL
• Selectable 2.5V
Output Voltage Via FAULT/MSEL Pin
MEM
the ATX 5V output in active states, or the ATX 5VSB in sleep
states.
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
The HIP6501A’s operating mode (active-state outputs or
sleep-state outputs) is selectable through two control pins:
S3 and S5. Further control of the logic governing activation
of different power modes is offered through two enabling
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting
• Adjustable Soft-Start Function Eliminates 5VSB
Perturbations
pins: EN3VDL and EN5VDL. In active states, the 3.3V
DUAL
• Pb-Free Available (RoHS Compliant)
linear regulator uses an external N-Channel pass MOSFET
to connect the output (V ) directly to the 3.3V input
OUT1
supplied by an ATX (or equivalent) power supply, while
incurring minimal losses. In sleep state, the 3.3V output
Pinout
HIP6501A (SOIC)
DUAL
TOP VIEW
is supplied from the ATX 5VSB through an NPN transistor,
also external to the controller. Active state power delivery for
16
1
2
3
4
5
6
7
8
VSEN2
5VSB
EN3VDL
3V3DLSB
the 2.5/3.3V
output is done through an external NPN
MEM
15 DRV2
transistor, or an NMOS switch for the 3.3V setting. In sleep
states, conduction on this output is transferred to an internal
14
13
12V
SS
3V3DL
pass transistor. The 5V
output is powered through two
DUAL
12 5VDL
EN5VDL
S3
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output,
while in active states, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. Similar to the
5VDLSB
11
10
9
DLA
S5
GND
FAULT/MSEL
3.3V
output, the operation of the 5V
output is
DUAL
DUAL
Ordering Information
dictated not only by the status of the S3 and S5 pins, but that
of the EN5VDL pin as well.
TEMP.
PKG.
PART NUMBER
RANGE (°C)
PACKAGE
16 Ld SOIC
DWG. #
HIP6501ACB
0 to 70
M16.15
M16.15
HIP6501ACBZ
(Note)
0 to 70
16 Ld SOIC
(Pb-free)
HIP6501AEVAL1
Evaluation Board
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
FN4749 Rev 6.00
December 30, 2004
Page 1 of 14
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