Datasheet > HIP6500CB

HIP6500CB

更新时间： 2024-01-30 03:08:57

品牌	Logo	应用领域
英特矽尔 - INTERSIL		控制器
页数	文件大小	规格书
15页	157K
描述
Multiple Linear Power Controller with ACPI Control Interface

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技术参数
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HIP6500CB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, MS-013-AC, SOIC-20
针数：	20	Reach Compliance Code：	not_compliant
风险等级：	5.79	Is Samacsys：	N
Base Number Matches：	1

HIP6500CB 数据手册

HIP6500

Data Sheet

December 1999

File Number 4774.1

Multiple Linear Power Controller with

ACPI Control Interface

Features

• Provides 5 ACPI-Controlled Voltages

The HIP6500 complements either an HIP6020 or an HIP6021

in ACPI-compliant designs for microprocessor and computer

applications. The IC integrates two linear controllers and two

regulators, switching, monitoring and control functions into a

20-pin SOIC package. One linear controller generates the

- 5V Active/Sleep (5V

DUAL

)

- 3.3V Active/Sleep (3.3V

)

DUAL

- 2.5V/3.3V Active/Sleep (2.5V

)

MEM

)

- 3.3V Always Present (3.3V

- 2.5V Clock (Active Only) (2.5V

CLK

)

3.3V

voltage plane from the ATX supply’s 5VSB output,

DUAL

• Excellent Output Voltage Regulation

powering the PCI slots through an external pass transistor

during sleep states (S3, S4/S5). A second transistor is used to

switch in the ATX 3.3V output for operation during S0 and

S1/S2 (active) operating states. The second linear controller

supplies the computer system’s 2.5V/3.3V memory power

through an external pass transistor in active states. During S3

state, an integrated pass transistor supplies the 2.5V/3.3V

- 3.3V

DUAL

Output: ±2.0% Over Temperature; Sleep

State Only

- 2.5V/3.3V

Output: ±2.0% Over Temperature; Both

MEM

Operational States (3.3V setting in sleep only)

- 2.5V

and 3.3V Output: ±2.0% Over Temperature

CLK

• Small Size

sleep power. A third controller powers up the 5V

plane by

DUAL

- Very Low External Component Count

switching in the ATX 5V output in active states, and the ATX

5VSB in sleep states. The two internal regulators consist of a

low current 3.3V sleep output and a dedicated, noise-free 2.5V

clock chip supply. The HIP6500’s operating mode (active

outputs or sleep outputs) is selectable through two digital

control pins, S3 and S5. Further control of the logic governing

activation of different power states is offered through two

configuration pins, EN3VDL and EN5VDL. In active state, the

• Selectable Memory Output Voltage Via FAULT/MSEL Pin

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

• Under-Voltage Monitoring of All Outputs with Centralized

FAULT Reporting and Temperature Shutdown

Applications

3.3V

linear regulator uses an external N-Channel pass

DUAL

•

MOSFET to connect the output directly to the 3.3V input

supplied by an ATX (or equivalent) power supply, for minimal

Motherboard Power Regulation for ACPI-Compliant

Computers

losses. In sleep state, power delivery on the 3.3V

output is

DUAL

Pinout

transferred to an NPN transistor, also external to the controller.

Active state power delivery for the 2.5/3.3V output is

HIP6500

(SOIC)

TOP VIEW

MEM

performed through an external NPN transistor, or an NMOS

switch for the 3.3V setting. In sleep state, conduction on this

output is transferred to an internal pass transistor. The 5V

DUAL

EN3VDL

VSEN2

5VSB

output is powered through two external MOS transistors. In

sleep states, a PMOS (or PNP) transistor conducts the current

from the ATX 5VSB output; while in active state, current flow is

transferred to an NMOS transistor connected to the ATX 5V

19 DRV2

3V3SB

12V

3V3DLSB

3V3DL

VCLK

output. Similar to the 3.3V

DUAL

output, the operation of the

output is dictated not only by the status of the S3 and

16 SS

DUAL

5VDL

S5 pins, but that of the EN5VDL pin as well. The 3.3V

5VDLSB

3V3

internal regulator is active for as long as the ATX 5VSB voltage

is applied to the chip, and derives its output current from the

EN5VDL

13 DLA

FAULT/MSEL

GND

5VSB pin. The 2.5V

output is only active during S0 and

CLK

S1/S2, and uses the 3V3 pin as input source for its internal

pass element.

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

20 Ld SOIC

HIP6500CB

0 to 70

M20.3

HIP6500EVAL1

Evaluation Board

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

12 3 4 5 6 7...15

中文翻译

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与HIP6500CB相关器件

型号	品牌	获取价格	描述	数据表
HIP6500EVAL1	INTERSIL	获取价格	Multiple Linear Power Controller with ACPI Control Interface
HIP6501	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface
HIP6501A	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface
HIP6501A_04	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface
HIP6501ACB	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface
HIP6501ACB	RENESAS	获取价格	4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, PLASTIC, MS-012-AC, SOIC-16
HIP6501ACBZ	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface
HIP6501ACBZ	RENESAS	获取价格	Triple Linear Power Controller with ACPI Control Interface; SOIC16; Temp Range: 0°
HIP6501ACBZ-T	RENESAS	获取价格	Triple Linear Power Controller with ACPI Control Interface; SOIC16; Temp Range: 0°
HIP6501AEVAL1	INTERSIL	获取价格	Triple Linear Power Controller with ACPI Control Interface

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