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HI-8588PDT PDF预览

HI-8588PDT

更新时间: 2024-11-13 22:38:35
品牌 Logo 应用领域
HOLTIC /
页数 文件大小 规格书
6页 171K
描述
ARINC 429 LINE RECEIVER

HI-8588PDT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:PLASTIC, DIP-8针数:8
Reach Compliance Code:compliantECCN代码:7A994
HTS代码:8542.39.00.01风险等级:5.09
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE RECEIVER
接口标准:ARINC 429JESD-30 代码:R-PDIP-T8
JESD-609代码:e0长度:9.779 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C最大输出低电流:0.0056 A
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):245
电源:5 V认证状态:Not Qualified
最大接收延迟:接收器位数:1
座面最大高度:4.699 mm子类别:Line Driver or Receivers
最大压摆率:6.3 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.62 mmBase Number Matches:1

HI-8588PDT 数据手册

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HI-8588  
January 2001  
DESCRIPTION  
PIN CONFIGURATION  
The HI-8588 is an ARINC 429 bus interface receiver and is  
available in a SO 8 pin package. The technology is  
analog/digital CMOS. The circuitry requires only a 5 volt  
supply.  
VCC 1  
TESTA 2  
RINB 3  
8 TESTB  
7 ROUTB  
6 ROUTA  
The ARINC bus can be connected directly to the chip. The  
typical 10 volt differential signal is translated and input to a  
window comparator and latch. The comparator levels are  
just below the standard 6.5 volt minimum ARINC data  
threshold and just above the standard 2.5 volt maximum  
ARINC nullthreshold.  
RINA 4  
5
GND  
SUPPLY VOLTAGES  
The TESTA and TESTB inputs bypass the analog for  
testing purposes. Also if TESTA and TESTB are both  
taken high, the analog powers down and the digital outputs  
tri-state allowing wire-or possibilities.  
vcc = 5.0V ± 5%  
Please refer to the HI-8588-10 for applications where an  
external resistance in series with the ARINC inputs is  
required for lightning protection or when the digital outputs  
need to be a logic zero rather than open circuit when  
TESTA and TESTBare both high.  
FUNCTION TABLE  
FEATURES  
! Direct ARINC 429 line receiver interface  
in a small outline package  
! Receiver input hystersis at least 2 volts  
! Test inputs that bypass analog input and  
PIN DESCRIPTION TABLE  
can power down and tri-state outputs  
PIN  
SYMBOL  
VCC  
FUNCTION  
SUPPLY  
DESCRIPTION  
5 VOLT SUPPLY  
! Plastic and ceramic package options -  
surface mount and DIP  
TESTA  
RINB  
LOGIC INPUT  
ARINC INPUT  
ARINC INPUT  
POWER  
CMOS  
RECEIVER B INPUT  
RECEIVER A INPUT  
GROUND  
RINA  
! Mil processing available  
GND  
ROUTA  
ROUTB  
TESTB  
LOGIC OUTPUT  
LOGIC OUTPUT  
LOGIC INPUT  
RECEIVER CMOS OUTPUT A  
RECEIVER CMOS OUTPUT B  
CMOS  
HOLT INTEGRATED CIRCUITS  
1
(DS8588 Rev. A)  
01/01  

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