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HI-3582ACJMF PDF预览

HI-3582ACJMF

更新时间: 2024-11-16 12:07:31
品牌 Logo 应用领域
HOLTIC /
页数 文件大小 规格书
17页 126K
描述
ARINC 429 3.3V Terminal IC with High-Speed Interface

HI-3582ACJMF 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.74uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

HI-3582ACJMF 数据手册

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HI-3582A, HI-3583A  
ARINC 429  
3.3V Terminal IC with High-Speed Interface  
July 2013  
GENERALDESCRIPTION  
APPLICATIONS  
The HI-3582A/HI-3583A from Holt Integrated Circuits are  
silicon gate CMOS devices for interfacing a 16-bit parallel  
data bus directly to the ARINC 429 serial bus. The  
HI-3582A/HI-3583A design offers a high-speed host CPU  
interface compared with the earlier HI-3582/HI-3583  
products. The device provides two receivers each with  
label recognition, 32 by 32 FIFO, and analog line receiver.  
Up to 16 labels may be programmed for each receiver.  
The independent transmitter has a 32 X 32 FIFO and a  
built-in line driver. The status of all three FIFOs can be  
monitored using the external status pins, or by polling the  
HI-3582A/HI-3583A status register. Other features include  
a programmable option of data or parity in the 32nd bit,  
and the ability to unscramble the 32 bit word. Also,  
versions are available with different values of input  
resistance and output resistance to allow users to more  
easily add external lightning protection circuitry.  
Avionics data communication  
Serial to parallel conversion  
Parallel to serial conversion  
PIN CONFIGURATIONS (Top View)  
(See page 14 for additional pin configuration)  
See Note below  
N/C  
-
1
2
3
4
5
6
7
8
9
48 - CWSTR  
47 - ENTX  
46 - N/C  
D/R1 -  
FF1 -  
HF1 -  
D/R2 -  
FF2 -  
HF2 -  
HI-3582APCI  
HI-3582APCT  
HI-3582APCM  
&
HI-3583APCI  
HI-3583APCT  
HI-3583APCM  
45 - V+  
44 - TXBOUT  
43 - TXAOUT  
42 - V-  
41 - N/C  
40 - FFT  
39 - HFT  
38 - TX/R  
37 - PL2  
SEL -  
EN1 -  
EN2 - 10  
N/C - 11  
BD15 - 12  
BD14 - 13  
BD13 - 14  
BD12 - 15  
BD11 - 16  
36 - PL1  
The 16-bit parallel data bus exchanges the 32-bit ARINC  
data word in two steps when either loading the transmitter  
or interrogating the receivers. The databus and all control  
signals are 3.3V CMOS compatible.  
35 - BD00  
34 - BD01  
33 - N/C  
The HI-3582A/HI-3583A apply the ARINC protocol to the  
receivers and transmitter. Timing is based on a 1 Mega-  
hertz clock.  
(Note: All 3 VDD pins must be connected to the same 3.3V supply)  
64 - Pin Plastic 9mm x 9mm  
Chip-Scale Package  
FEATURES  
·
·
·
·
ARINC specification 429 compatible  
High-speed 3.3V logic interface  
Dual receiver and transmitter interface  
Analog line driver and receivers connect directly to  
ARINC bus  
Programmable label recognition  
On-chip 16 label memory for each receiver  
32 x 32 FIFOs each receiver and transmitter  
Independent data rate selection for transmitter and  
each receiver  
Status register  
Data scramble control  
32nd transmit bit can be data or parity  
Self test mode  
Low power  
FF1 -  
HF1 -  
D/R2 -  
FF2 -  
HF2 -  
SEL -  
EN1 -  
EN2 -  
BD15 -  
BD14 - 10  
BD13 - 11  
BD12 - 12  
BD11 - 13  
1
2
3
4
5
6
7
8
9
39 - N/C  
38 - CWSTR  
37 - ENTX  
36 - V+  
35 - TXBOUT  
34 - TXAOUT  
33 - V-  
32 - FFT  
31 - HFT  
30 - TX/R  
29 - PL2  
28 - PL1  
HI-3582APQI  
HI-3582APQT  
HI-3582APQM  
&
HI-3583APQI  
HI-3583APQT  
HI-3583APQM  
·
·
·
·
·
·
·
·
·
·
27 - BD00  
Industrial & extended temperature ranges  
52 - Pin Plastic Quad Flat Pack (PQFP)  
HOLT INTEGRATED CIRCUITS  
www.holtic.com  
(DS3582A Rev. C)  
07/13  

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