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HEF4040B-Q100 PDF预览

HEF4040B-Q100

更新时间: 2024-09-24 01:22:43
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
13页 680K
描述
12-stage binary ripple counter

HEF4040B-Q100 数据手册

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HEF4040B-Q100  
12-stage binary ripple counter  
Rev. 1 — 4 April 2013  
Product data sheet  
1. General description  
The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an  
overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to  
Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears  
all counter stages and forces all outputs LOW, independent of CP. Each counter stage is  
a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to  
its Schmitt trigger action.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 3) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 3)  
Specified from 40 C to +85 C  
Tolerant of slow clock rise and fall time  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Complies with JEDEC standard JESD 13-B  
3. Applications  
Frequency dividing circuits  
Time delay circuits  
Control counters  

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