Datasheet > HEF4027BT-Q100J

HEF4027BT-Q100J

更新时间： 2024-09-23 21:18:11

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
13页	105K
描述
HEF4027B-Q100 - Dual JK flip-flop SOP 16-Pin

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HEF4027BT-Q100J 技术参数

HEF4027B-Q100

Dual JK flip-flop

Rev. 1 — 26 June 2013

Product data sheet

1. General description

The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent

set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted

when CP is LOW, and transferred to the output on the positive-going edge of the clock.

The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are

independent and override the J, K, and CP inputs. The outputs are buffered for best

system performance. Schmitt trigger action makes the clock input highly tolerant of slower

rise and fall times.

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 3) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 3)

 Specified from 40 C to +85 C

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 ESD protection:

 MIL-STD-833, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Complies with JEDEC standard JESD 13-B

3. Applications

 Registers

 Counters

 Control circuits

12 3 4 5 6 7...13

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