Datasheet > HEF4027BT-Q100

HEF4027BT-Q100

更新时间： 2024-09-24 11:13:15

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
11页	213K
描述
Dual JK flip-flopProduction

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HEF4027BT-Q100 数据手册

HEF4027B-Q100

Dual JK flip-flop

Rev. 2 — 7 December 2021

Product data sheet

1. General description

The HEF4027B-Q100 is a dual positive-edge triggered JK flip-flop featuring independent set direct

(nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data

is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the

clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the

nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant

to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V_DD

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 3) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 3)

Specified from -40 °C to +85 °C

•

Wide supply voltage range from 3.0 V to 15.0 V

CMOS low power dissipation

High noise immunity

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

ESD protection:

•

MIL-STD-833, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

Complies with JEDEC standard JESD 13-B

3. Applications

•

Registers

Counters

Control circuits

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

Name

Description

Version

HEF4027BT-Q100 -40 °C to +85 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

12 3 4 5 6 7...11

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