Datasheet > HEF4020B_08

HEF4020B_08

更新时间： 2024-11-21 05:35:43

品牌	Logo	应用领域
恩智浦 - NXP		计数器
页数	文件大小	规格书
13页	88K
描述
14-stage binary counter

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HEF4020B_08 数据手册

HEF4020B

14-stage binary counter

Rev. 04 — 4 December 2008

Product data sheet

1. General description

The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to

Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears

all counter stages and forces all outputs LOW, independent of the state of CP. Each

counter stage is a static toggle ﬂip-ﬂop. A feature of the device is its high speed

(typ. 35 MHz at V_DD= 15 V).

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input. It is

also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features

I High speed operation

I Fully static operation

I 5 V, 10 V, and 15 V parametric ratings

I Standardized symmetrical output characteristics

I Operates across the full industrial temperature range −40 °C to +85 °C

I Complies with JEDEC standard JESD 13-B

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

3. Applications

I Industrial

4. Ordering information

Table 1.

Ordering information

All types operate from −40 °C to +85 °C.

Type number Package

Name

DIP16

SO16

Description

Version

HEF4020BP

HEF4020BT

plastic dual in-line package; 16-leads (300 mil)

plastic small outline package; 16 leads; body width 3.9 mm

SOT38-4

SOT109-1

12 3 4 5 6 7...13

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